A.11 Spd Contents For Mvme7100Et Boards - SMART Embedded Computing MVME7100ET Programmer's Reference Manual

A.11 SPD Contents for MVME7100ET Boards

The following table describes the SPD data to be programmed into U50 and U51.
Table A-6
Value
00 (0x00)
01 (0x01)
02 (0x02)
03 (0x03)
04 (0x04)
05 (0x05)
06 (0x06)
07 (0x07)
08 (0x08)
09 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
16 (0x10)
MVME7100ET Single Board Computer Programmer's Reference (6806800K88C)
SPD Contents
Offset Description
Number of Serial PD Bytes written during module production: 0x80 = 128
bytes.
80
Refer to Note
Total Number of Bytes in Serial PD Device: 0x08 = 256 bytes.
08
Refer to Note
Fundamental Memory Type (FPM, EDO, SDRAM): 0x08 = DDR2
08
SDRAM
0E Number of Row Addresses on this assembly: 0x0E = A0-A13
0A Number of Column Addresses on this assembly: 0x0A = A0-A9
00 Number of DIMM Banks: 0x00 = one bank
48 Data Width of this assembly: 0x48 = 72 bits
00 Reserved
05 Voltage Interface Level of this assembly: 0x05 = SSTL 1.8 V
SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X:
0x30 = 3.0ns.
30
Refer to Note
SDRAM Access time from Clock at Maximum Supported CAS Latency
(CL), CL=X: 0x45 = 0.45ns.
45
Refer to Note
02 DIMM configuration type (Non-parity, Parity or ECC): 0x02 = ECC
Refresh Rate/Type: 0x81= 3.9us.
81
Refer to Notes 3 and 4.
08 Primary SDRAM Width: 0x08 = 8 bits
08 Error Checking SDRAM Width: 0x08 = 8 bits
00 Reserved
SDRAM Device Attributes - Burst Lengths Supported: 0x0C = 4, and 8
0C
burst lengths
Programmable Configuration Data
1
.
2
.
3
.
3
.
77