Create And Configure The Pll - Arrow CYC1000 User Manual

5.2.4.2 Click "Add". When the Save IP Variation window appears, enter the file name variation
as PLL and select VHDL (Verilog can be used as well). Both Verilog and VHDL schematics
will be created.
5.2.4.3 Click "OK".

5.2.5 Create and Configure the PLL

The next step is to configure the PLL component that we just named.
5.2.5.1 Enter the PLL reference clock frequency to match the clock input on the CYC1000 Board.
Since we have a 12 MHz coming into the FPGA, the inclk0 input will be 12MHz.
The setting should look like this:
5.2.5.2 Click "Next".
CYC1000 User Guide
Page | 31
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January 2020