Related Manuals for Arrow BeMicro CV A9
Summary of Contents for Arrow BeMicro CV A9
- Page 1 BeMicro CV A9 FPGA Development Board Hardware Reference Guide Altera's 28nm Low Cost FPGA Solution...
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Page 2: Table Of Contents
Table of Contents Overview ..........................3 General Description ........................3 Board Component Features ......................4 Development Board Block Diagram .................... 5 Handling the Board ........................7 Board Components ........................7 Cyclone V E FPGA ........................9 Configuration Options ......................... 9 Clock Circuitry ........................... -
Page 3: Overview
Arrow BeScope digital oscilloscope, SDRstick SDR front-end boards, and the Terasic MTL LCD module. For a complete list of products compatible with BeMicro CV A9 board, see the BeMicro CV A9 Partner Pack at http://www.arrow.com/bemicro. Users can easily migrate existing designs from BeMicro SDK or BeMicro CV to BeMicro CV A9. -
Page 4: Board Component Features
Board Component Features The BeMicro CV A9 board features the following major component blocks: Cyclone V E FPGA (5CEFA9F23C8N) in a 484-pin FineLine BGA (FBGA) • 113,560 adaptive logic modules (ALMs) equivalent to 301,000 LEs • 12,200 Kbit (Kb) M10K and 1,717 Kb MLAB memory •... -
Page 5: Development Board Block Diagram
Development Board Block Diagram Figure 1-1 shows a block diagram of the BeMicro CV A9 FPGA development board. Figure 1-1: BeMicro CV A9 Block Diagram... - Page 6 Figure 1-2 shows a top view of the BeMicro CV A9 FPGA development board. Figure 1-2: Top View of BeMicro CV A9 Development Board. Figure 1-3 shows a bottom view of the BeMicro CV A9 FPGA development board. Figure 1-3: Bottom View BeMicro CV A9 Development Board...
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Page 7: Handling The Board
Handling the Board When handling the board, it is important to observe the following static discharge precaution: Without proper anti-static handling, the board can be damaged. Therefore, use anti-static handling precautions when touching the board. 2. Board Components This chapter introduces the major components on the Be Micro CV A9 FPGA development board. - Page 8 Figure 2-2: Major component locations, Bottom View This chapter includes the following sections: • Cyclone V E FPGA • Configuration Options • Clock Circuitry • General User Input / Output • DDR3 Memory • Ethernet Interface • EEPROM • Micro SD Card •...
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Page 9: Cyclone V E Fpga
The PROM supports the AS x4 configuration mode. By default, the BeMicro CV A9 board is set up to configure via AS x 4 configuration mode. Resistors R97 and R98 allow selection between AS Fast and AS Standard modes. -
Page 10: Clock Circuitry
Figure 2-3: Active Serial x4 Configuration Interface Clock Circuitry The development board includes two oscillators with frequencies of 24 MHz and 50 MHz. Table 2–2 lists the oscillators, their I/O standard, and voltages required for the development board. Table 2-2: BeMico CV On-board oscillators Board Schematic Signal Frequency... - Page 11 Table 2-3: LED Board Reference Information Board FPGA Pin Schematic Signal Functional Reference Number Name Standard Description LED1 USER_LED1 1.5 V Green User LED LED2 USER_LED2 1.5 V Green User LED LED3 USER_LED3 1.5 V Green User LED LED4 USER_LED4 1.5 V Green User LED LED5...
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Page 12: Ddr3 Memory
User-Defined DIP Switch Board reference SW3 is a 4-place DIP switch. This switch is user-defined and provides additional FPGA input control. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected. There are no board-specific functions for this switch. - Page 13 Table 2-7: DDR3 pin assignments, signal names, and functions FPGA Pin Schematic Signal I/O Standard Description Number Name DDR3_A0 1.5V SSTL Class I Address bus DDR3_A1 1.5V SSTL Class I Address bus DDR3_A2 1.5V SSTL Class I Address bus DDR3_A3 1.5V SSTL Class I Address bus DDR3_A4...
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Page 14: Ethernet Interface
Write Enable Ethernet Interface The BeMicro CV A9 board includes a Micrel KSZ9021 10/100/1000 Ethernet PHY and RJ45 connector. Altera’s Triple Speed Ethernet MAC soft IP core can be implemented inside the Cyclone V FPGA to connect to the PHY through its RGMII interface. -
Page 15: Eeprom
Note 1: I/O voltage for this interface is selectable using the VCCIO_SEL jumper Micro SD Card The BeMicro CV A9 board includes a Micro SD card slot with x4 data interface to the FPGA. Table 2–10 lists the FPGA pin assignments, signal names, and functions for the Micro SD card. -
Page 16: Pin Prototyping Headers
Note 1: I/O voltage for this interface is selectable using the VCCIO_SEL jumper 40 Pin Prototyping Headers The BeMicro CV A9 board includes two 2×20 prototyping headers. The FPGA user I/O pins are routed directly to the headers for design testing, debugging, verification and prototyping. - Page 17 2.5 V or 3.3 V DIFF_RX_N9 2.5 V or 3.3 V DIFF_RX_P8 2.5 V or 3.3 V DIFF_RX_N8 2.5 V or 3.3 V DIFF_RX_P7 2.5 V or 3.3 V DIFF_RX_N7 2.5 V or 3.3 V DIFF_RX_P6 2.5 V or 3.3 V DIFF_RX_N6 VCC3P3 2.5 V or 3.3 V...
- Page 18 Table 2-12: Board Reference Information for 40 Pin Prototyping Header J4 FPGA Pin Number Schematic Signal Name I/O Standard J4 Pin Number VCC3P3 VCC3P3 GPIO_A 2.5 V or 3.3 V GPIO_B 2.5 V or 3.3 V LVDS_TX_E_N4 2.5 V or 3.3 V LVDS_TX_E_P4 2.5 V or 3.3 V LVDS_TX_E_N3...
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Page 19: Pin Card Edge Connector
Ensure that any card you connect to the BeMicro 80 Pin Card Edge Connector is intended for that particular BeMicro variant. For further guidance, consult the add-on card’s documentation, along with the BeMicro CV A9 Schematic at https://parts.arrow.com/item/detail/arrow-development-tools/bemicrocva9 Table 2–13 lists the card edge connector J2 pin assignments, signal names, and functions. - Page 20 EG_P35 2.5 V or 3.3 V EG_P2 2.5 V or 3.3 V EG_P36 2.5 V or 3.3 V AA13 EG_P3 2.5 V or 3.3 V AA14 EG_P4 2.5 V or 3.3 V EG_P37 2.5 V or 3.3 V EG_P5 2.5 V or 3.3 V EG_P38 2.5 V or 3.3 V AB15...
- Page 21 EG_P16 2.5 V or 3.3 V EG_P49 2.5 V or 3.3 V AB20 EG_P17 2.5 V or 3.3 V EG_P50 2.5 V or 3.3 V EG_P18 2.5 V or 3.3 V AA20 EG_P19 2.5 V or 3.3 V EG_P51 2.5 V or 3.3 V AB22 EG_P20 2.5 V or 3.3 V...
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Page 22: Power Supply
VCCIO_POWER 2.5 or 3.3 FPGA I/O bank power (Banks 3A, 3B, 4A, 5B), I/O pre-driver power (Banks 3A, 3B, 5A, 5B) The BeMicro CV A9 board supports VCCIO of 2.5V or 3.3V for I/O Banks 3A, 3B, 4A and 5B. -
Page 23: Additional Information
Connect pins 1 and 2 3. Additional Information This chapter provides additional information about the document. Board Revision History The following table lists the versions of all releases of the Arrow Electronics BeMicro CV A9 Cyclone V FPGA Development Board. Release Date Version... -
Page 24: Document Revision History
Document Revision History Date Version Description September 2014 Initial Release June 2015 Updated pin descriptions in Table 2-8; other minor updates & corrections For more information on the BeMicro CV A9 Cyclone V E Development Board, visit https://parts.arrow.com/item/detail/arrow-development-tools/bemicrocva9 http://www.alterawiki.com/wiki/BeMicro_CV_A9...