Sdram Memory; Figure 8 - Sdram Connections - Arrow CYC1000 User Manual

Board Reference
SEN_INT1
SEN_INT2
SEN_SDI
SEN_SDO
SEN_SPC
SEN_CS
*For SPI connection

3.3.4 SDRAM Memory

The CYC1000 board supports 64MBit (default version) or up to 256MBit (customized version)
SDRAM which can operate up to 166 MHz clock frequency. Below are the connections and pinning
of the SDRAM used in the CYCX1000.
Board Reference
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
RAS
CAS
WE
CS
CYC1000 User Guide
FPGA Pin No.
PIN_B1 Interrupt 1
PIN_C2 Interrupt 2
PIN_G2 Data In (MOSI)*
PIN_G1 Data Out (MISO)*
PIN_F3 Clock*
PIN_D1 Chip Select*
Figure 8 – SDRAM Connections
FPGA Pin No.
PIN_A3 SDRAM Address [0]
PIN_B5 SDRAM Address [1]
PIN_B4 SDRAM Address [2]
PIN_B3 SDRAM Address [3]
PIN_C3 SDRAM Address [4]
PIN_D3 SDRAM Address [5]
PIN_E6 SDRAM Address [6]
PIN_E7 SDRAM Address [7]
PIN_D6 SDRAM Address [8]
PIN_D8 SDRAM Address [9]
PIN_A5 SDRAM Address [10]
PIN_E8 SDRAM Address [11]
PIN_A2 SDRAM Address [12]
PIN_C6 SDRAM Address [13]
PIN_A4 SDRAM Bank Address [0]
PIN_B6 SDRAM Bank Address [1]
PIN_B7 SDRAM Row Address Strobe
PIN_C8 SDRAM Column Address Strobe
PIN_A7 SDRAM Write Enable
PIN_A6 SDRAM Chip Select
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Description
Description
I/O Standard
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
I/O Standard
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
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January 2020