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11.3.2 Access to the SPC 4-2 with LOCK Activated
Description
In the dual-port RAM certain areas are modified both by the FLC and by the MS;
these are cells in the SAP list. To avoid data conflicts between write and read-
modify-write access, the SPC 4-2 has a lock mechanism (see also the hardware
description, section 5.1.2). If the FLC wants to access this area, it must first check
whether the memory is 'locked' by the MS. For this purpose, there is a symbolic
memory cell 'Mem-Lock' (in other words, a reserved address), in the address area
of the parameter latches. The value of this cell is switched to bit(0) of the data bus
when it is read.
If the value = 'logical 0', the memory bus is not locked by the microsequencer and
the FLC can access the RAM in the next cycle. As soon as the cell is read, an
internal lock flag is set. With this flag, the dual-port RAM controller recognizes that
there has been access via the interface with LOCK activated. If the MS also wants
to access with LOCK activated at this point in time, the dual-port RAM controller
(DPC) stops the MS. As a result, if the FLC reads 'logical 0' when accessing the
mem-lock cell, the next accesses are made with the lock activated until the flag is
reset.
If the mem-lock cell returns a 'logical 1', the MS is currently accessing the RAM
with LOCK activated. In this case, the FLC must poll the mem-lock cell until a
'logical 0' is returned. Generally, the bit will be reset the second time it is read,
since MS access is considerably faster than read access via the external interface.
Notice:
In particular in cases is which the local microprocessor has a much faster clock
rate than the SPC 4-2, it cannot be assumed that local microsequencer access will
be faster than access by the microprocessor. Polling the mem-lock cell is
absolutely necessary here.
The state of the MEM-LOCK bit is entered in the status register. After access with
lock activated, the bit must be reset. This achieved by a byte cycle to the mem-lock
cell, with don't care data.
Note
The duration of the lock must be less than the maximum selected T ID1 or T SLOT
of the master station. If this condition is not met, it is possible that the SPC 4-2 will
no longer recognize a frame.
PROFIBUS Controller SPC 4®-2 LF
C79000-G8976-C157-3
Processor Interface
135
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