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11.7
Intel /Siemens 8051 (synchronous) etc.
11.7.1 Circuit Diagram
20MHz
CLK
WR
RD
INT0
80C32
20/16MHz
ALE
A / D 7...0
Port 0
AB 15...8
Port 2
PSEN
Reset
Figure 11-3
Circuit Diagram
INTEL, CPU Basis 80C51/2 (80C32), microcontrollers from various vendors
•
Synchronous (rigid) bus; timing without evaluation of the READY signal
Typ
Mode
•
8-bit multiplexed bus ADB(7-0),
The following can be connected:
•
Microcontroller families, e.g. INTEL, SIEMENS, PHILIPS ...
Address decoder on the SPC 4-2 is activated; CS signal is supplied internally:
•
0
1
The lower address bits A(7-0) are stored in an internal address latch with the ALE
signal. On the SPC 4-2 , the internal CS decoder is activated and generates its
own CS signal from the addresses A(9-0).
•
The integrated address decoder is hardwired so that the SPC 4-2 must always be
addressed at the fixed address at A(7...0)=0000 00xxb , and the SPC 4-2 selects
the corresponding address window from the signals A(1,0) .
•
In this mode, the CS pin (XCS) must be connected to VDD (high potential)
Wiring: Connection diagrams are stipulated by the specification.
(synchronous
•
ADB(7-0) to SPC 4-2 pin DB(7-0), AB(15-8) to SPC 4-2 pin
INTEL)
•
AB(7-0) and SPC 4-2 pin AB (9,8) connected to VSS.
PROFIBUS Controller SPC 4®-2 LF
C79000-G8976-C157-3
80C32 system with ext. memory (C32 mode)
Address
latch
AB 15...0
EPROM
RAM
64kB
32kB
RD WR
XWR
XRD
X/INT
DB 7..0
Data
DB 7..0
Address latch
AB 0..1
Window sel.
(0000 00XX BIN)
AB 2..7
CS decoder
AB8
AB9
TYP
Address
decoder
1K
1K 1K
GND
Processor Interface
Clock generator
48 MHz
RTS
TxD
RxD
XCTS
1K
SPC4
GND
SPC4
Mode
Reset
XCS
3K
3K
3
3
CPU
VDD
139
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