Siemens SIMATIC NET SPC 4-2 LF Manual
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Siemens SIMATIC NET SPC 4-2 LF Manual

Siemens SIMATIC NET SPC 4-2 LF Manual

Profibus controller
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SIMATIC NET
PROFIBUS Controller
®
SPC 4
-2 LF
Manual
C79000-G8976-C157-3
Release 12/2006
Contents
Introduction
Functional Overview
Pin Assignment
Memory Assignment
FLC Interface
DP Interface
ASIC Interface
Asynchronous Interface
Synchronous Interface
Clock Pulses
Processor Interface
Technical Specifications
Package
References
Addresses
Appendix
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

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Summary of Contents for Siemens SIMATIC NET SPC 4-2 LF

  • Page 1 Contents Introduction Functional Overview SIMATIC NET Pin Assignment PROFIBUS Controller ® SPC 4 -2 LF Memory Assignment FLC Interface Manual DP Interface ASIC Interface Asynchronous Interface Synchronous Interface Clock Pulses Processor Interface Technical Specifications Package References Addresses Appendix C79000-G8976-C157-3 Release 12/2006...
  • Page 2 Copyright © Siemens AG, 2001 bis 2006 Disclaimer We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement.
  • Page 3 This product may only be used for the applications described in the catalog or the technical description, and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens. This product can only function correctly and safely if it is transported, stored, set up, and installed correctly, and operated and maintained as recommended.
  • Page 4 Prior to Commissioning Prior to commissioning, note the following warning: Caution Prior to startup read the relevant documentation. For ordering data of the documentation, please refer to catalogs or contact your local Siemens representative. PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 5: Table Of Contents

    Contents Introduction........................9 Functional Overview ....................11 Pin Assignment ......................15 Memory Assignment ....................19 Addressing the SPC 4-2 ..................20 Structure of the Internal RAM ................22 4.2.1 Overview......................22 4.2.2 RAM Parameter Block ..................22 4.2.3 SAP List ......................24 4.2.4 Data Areas in the Internal RAM.................
  • Page 6 7.1.2 Baudrate Register....................65 7.1.3 BEGIN-PTR Register..................67 7.1.4 UMBR-PTR Register ..................67 7.1.5 BASE-PTR Register ..................67 7.1.6 TRDY Register....................68 7.1.7 PREAMBLE Register..................68 7.1.8 SYN-Time Register.................... 69 7.1.9 Delay-Timer Register..................69 7.1.10 Factor-Delay-Timer-Clock Register ..............70 7.1.11 Mode Register ....................70 7.1.12 Status Register ....................
  • Page 7 11.4.2 XHOLDTOKEN ....................136 11.5 Interrupt Timing....................137 11.6 Reset Timing....................138 11.7 Intel /Siemens 8051 (synchronous) etc............139 11.7.1 Circuit Diagram ....................139 11.7.2 Timing 80C32 ....................140 11.8 Intel X86 (asynchronous)................. 142 11.8.1 Circuit Diagram ....................142 11.8.2 Timing x86 .......................
  • Page 8 References ........................167 Addresses ........................169 15.1 PNO ......................... 170 15.2 Contacts in the Interface Center..............171 Appendix ........................173 16.1 Server Software for the SPC 4-2 ..............174 16.2 SIM1......................... 176 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 9: Introduction

    Introduction PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 10 ASICs For simple and fast digital exchange between programmable logic controllers, Siemens offers users various ASICs. These ASICs either support or handle the entire data exchange between the automation stations according to the PROFIBUS standards and guidelines DIN 19245 Part 1, Part 2, Part 3 and PROFIBUS PA ®...

  • Page 11: Functional Overview

    Functional Overview PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 12 Apart from the bus drivers, the SPC 4-2 contains the entire PROFIBUS peripherals. The additional processor does not need to provide a hardware timer to process the bus protocol. Baud rates from 9.6 kbit/s to 12 Mbit/s are supported. The SIM 1 ASIC is an ideal extension for PROFIBUS PA.
  • Page 13 Functional Overview Compatibility with SPC 4/4-1 ® ® ® The SPC 4 -2 is compatible with the ASIC SPC 4 and SPC 4 1. This compatibility includes the mechanical and electrical properties as well as the functions used via a software interface. Additional properties of the SPC 4-2 ●...
  • Page 14 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 15: Pin Assignment

    Pin Assignment PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 16 The SPC 4-2 has a 44-pin plastic quad flat package housing (see Chapter 11). The pin assignment is described in Table 3-1 Pin Assignment Note: All signals that start with X.. are LOW-active Signal name Description Source / Dest Processor Variant Chip select C32 mode: connect...
  • Page 17 Pin Assignment Signal name Description Source / Dest Processor Variant Data bus CPU, memory /address bus multiplexed Data bus CPU, memory Otherwise: data/address bus Data bus CPU, memory separate MODE Timing format of the processor System interface (see Mode Table) Address latch enable C32 mode: ALE Address strobe with Motorola (in...
  • Page 18 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 19: Memory Assignment

    Memory Assignment PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 20: Addressing The Spc 4-2

    Addressing the SPC 4-2 From the user perspective, the 3-Kbyte internal dual-port RAM and the internal latches occupy a 1-Kbyte address space. Parts of the internal RAM are located directly in the address range of the microprocessor, the other parts can be addressed using a window mechanism, see Figure 4-1 Micro- processor...
  • Page 21 Memory Assignment Address Window With the lower address window, the FLC can access the first 512 (2 x 256) bytes of the RAM physically without needing to load the base pointer. The advantage of this is that the FLC can access the general parameters or the SAP list directly without first needing to load the base pointer.

  • Page 22: Structure Of The Internal Ram

    Structure of the Internal RAM 4.2.1 Overview Figure Figure 4-3 shows the structure of the internal 3 Kbyte RAM of the SPC 4-2. The entire memory area made up of segments of 8 bytes (or 16 bytes in the extended SPC 4-2 mode) is divided into different areas. Byte 0 Segment 0 RAM parameters...
  • Page 23 Memory Assignment Address Name Access Meaning IND-WP- The write pointer for indication preprocessing points to the RD/WR next free segment that follows the last request frame received even when no indication "IND" has been received. The IND-WP-PRE pointer allows a fast slave reaction (for example for PROFIBUS DP).

  • Page 24: Sap List

    Access to the parameter registers or the internal RAM require not only the correct connection of the relevant address bits but also the connection of an XCS signal to the SPC 4-2. In addition to this, the XREADY signal of the SPC 4-2 must be taken into account or suitable wait states must be created.
  • Page 25 Memory Assignment Caution After initialization in the offline mode, both pointers must be set to the required start of the range. THEY CANNOT BE MODIFIED DYNAMICALLY; in other words, to modify the memory assignment, the SPC 4-2 must be changed to offline. A change in the order of the pointers leads to an incorrect response of the SPC 4-2 related to the individual memory areas.

  • Page 26: Addressing Using The Memory Window

    4.2.5 Addressing Using the Memory Window When addressing the SPC 4-2, the physical address of the integrated RAM is formed via the second address window (200h to 2FFh) from the base pointer, the segment address for the indication queue and the lower 8 bits of the address bus. The base pointer is added to the address of the address that is shifted by three or four bit positions, see Figure 4-5.
  • Page 27 Memory Assignment Base point register Address bus bits 7 ... 0 Byte address within a segment 12-bit RAM address Figure 4-6 Calculating Physical RAM Address in the Extended SPC 4-2 Mode PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 28: Assignment Of The Parameter Registers

    Assignment of the Parameter Registers It is only possible to access the internal parameter registers (in other words, the memory cells that intervene directly in the controller) using the address window 300h to 3FFh on the SPC 4-2. These cells can either only be read or only be written and have different functions. In the Motorola mode, the SPC 4-2 swaps addresses for access to the address range starting at 300H (word register);...
  • Page 29 Memory Assignment Address Name Meaning ( READ access ! ) Intel /Motorola Int-Req-Reg 7..0 Interrupt controller register Int-Req-Reg 15..8 Int-Reg 7..0 Int-Reg 15..8 Status-Reg 7..0 Status Register Status-Reg 15..8 Delay 7..0 Delay timer register, current counter reading Delay 15..8 reserved reserved reserved reserved...
  • Page 30 Address Name Meaning (write access !) Intel/Motorola Int-Mask-Reg 7..0 Interrupt controller register Int-Mask-Reg 15..8 Int-Ack-Reg 7..0 Int-Ack-Reg 15..8 TSLOT 7..0 Settings for the wait-to-receive time TSLOT 13..8 BR-REG 7..0 Setting of the dividing factor BR-REG 10..8 For generating the baud rate TID1 7..0 TID1 10..8 FAKT-DEL-CLK 7..0...
  • Page 31 Memory Assignment Address Name Meaning (write access !) Intel/Motorola Error-Hi-Reg 15..8 Writing to this register also deletes Error-Hi-Reg and Error- Lo-Reg Error-Lo-Reg 7..0 Writing to this register also deletes Error-Hi-Reg and Error- Lo-Reg Table 4-8 Assignment of the Internal Parameter Registers (Only for Write Access) PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 32 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 33: Flc Interface

    FLC Interface PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 34: Sap List

    SAP List 5.1.1 Structure of the SAP List The SAP list is made up as follows: ● 5 SM-SAPs (System Management Service Access Point) each 5 bytes long ● DEFAULT-SAP (Service Access Point) with 16 bytes 64 SAPs each 5 bytes long PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 35 FLC Interface Address Name register Meaning Control Byte Bit information Request-SA Request source address reserved reserved Reply-Update-Ptr/ Pointer to the reply buffer SDN-DDB/-Tln-Tab-Ptr 1DH - 21H analogous to SM1 analogous to SM1 22H - 26H analogous to SM1 analogous to SM1 27H - 2BH analogous to SM1 analogous to SM1...
  • Page 36 Service Access Points In the FLC, a data transfer service is handled using a Service Access Point, SAP). On each node, up to 64 SAPs are possible (SAP [0..63] and the DEFAULT SAP). Communication between a DEFAULT SAP and a SAP is possible. The SPC 4-2 performs a validation of the request SSAPs.

  • Page 37: Control Byte

    FLC Interface 5.1.2 Control Byte Bit Position Meaning SDN/ DDB RS/RA or IN USE Buffer available Control byte locked filter Bits 0- Buffer available These three bits are used as a counter for resources provided externally. The FLC increments the 3 bits as soon as a resource is available.

  • Page 38: Request Sa

    5.1.3 Request SA Description The received SA is compared with this entry. If it does not match, the SPC 4-2 sets the event flag no service activated (RS) and replies with service access point blocked [RA] in the PA mode and no service activated [RS] in the PROFIBUS mode (SD1 response).
  • Page 39 FLC Interface Bit 0-3 Access Value Access Protection 0H = 1H = SDN-Low 2H = SDN-High 3H = SDN-Low/High 4H = 5H = SDA-Low 6H = SDA-High 7H = SDA-Low/High 8H = SRD-Low/High DDBREQ DDB-RES-Low/High 9H = SRD Low AH = SRD-High BH = SRD-Low/High...

  • Page 40: Reply-Update-Ptr/ Sdn-/Ddb-Tln-Tab-Ptr

    5.1.6 Reply-Update-Ptr/ SDN-/DDB-Tln-Tab-Ptr: The "Reply-Update-Ptr/ SDN-/DDB-Tln-Tab-Ptr" pointer points to the indication reply buffer or to the SDN/DDB-Tln list (see also SDN-/DDB filter). The data buffers must be located above the UMBR-PTR in the SPC 4-2. Structure The structure of the SDN-/DDB-Tln list is described in the following table: SDN-/DDB-Tln-List (Optional tab-data- 8 bits...

  • Page 41: Special Features Of The Default Sap

    FLC Interface Sending over the Default SAP To allow the sender to use the DEFAULT SAP, "req-ssap=0FFh" and the extension bit "req-sa"=0 must be entered in the node table at the receiving end. In all other cases, the extension bit "req-sa"=1 is set. 5.1.7 Special Features of the DEFAULT SAP When using the DP mode, the following entries can also be processed in the SAP...
  • Page 42 ● Active-Group-Ident: This byte encodes the membership of the DP slave in a maximum of 8 groups. The Active-Group-Ident is ANDed bit-by-bit with the Group-Select-Byte of a received global-control frame (GCT). The DP slave is addressed when the AND logic operation returns a value other than zero in at least one position. If the group-select byte of the GCT is zero, all DP slaves are addressed.

  • Page 43: Sm-Sap List

    FLC Interface SM-SAP List Structure of the SM-SAP Entries The structure of the SM-SAP entries is analogous to those with normal SAPs. Register Meaning Control Byte Bit information Request-SA Request source address reserved reserved Reply-Update-Ptr/SDN-DDB/-Tln-Tab-Ptr Pointer to the reply buffer Unnecessary SAPs should be deactivated, for example with Request-SA=7Fh.

  • Page 44: Indication Queue

    Indication Queue 5.3.1 Description Function If the SPC 4-2 receives a frame, it enters the frame header in the indication queue and then checks the free length in the queue (this is possible because one segment must always remain free). If at least one segment (8 or 16 bytes) is free (in addition to the special free segment), it continues reception and enters the data in the queue as long as there is free memory available.
  • Page 45 FLC Interface Indication queue BEGINN-PTR Indication block IND-RD Response resp-buf-ptr (8 Bit) header indic-status Indication block n-1 (2 bytes) (00 valid, CFH invalid) IND-WR Request req-data-length header rem-adr (6 bytes) loc-adr co-code Indication block n rem-sap loc-sap Request buffer (max. 246 bytes) Figure 5-6 Structure of the Indication Queue...

  • Page 46: Structure Of The Indication Block

    5.3.2 Structure of the Indication Block Response header Byte 0 resp- This pointer points to the swapped-out response buffer (in the reply-on-indication-blocks buf-ptr area, refer to the memory area distribution). It is copied by the SPC 4-2 from the SAP list. Byte 1 indic- Here, the SPC 4-2 enters the status 00 for a 'valid indication'.

  • Page 47: Reply-On-Indication Blocks

    FLC Interface Reply-on-Indication Blocks 5.4.1 Description Function The FLC must provide the reply data in the buffers of the reply-on-indication blocks. If reply data are requested, the SPC 4-2 fetches the reply update pointer from the relevant SAP lists and sends the data from the reply buffer. Once the job is completed, the SPC 4-2 indicates the job by entering the status (valid indication) in the response header, setting the write pointer to the next free segment, and generating the IND interrupt.

  • Page 48: Structure Of The Reply-On-Indication Blocks

    5.4.2 Structure of the Reply-on-Indication Blocks Area of reply-on-indication blocks Indication block UMBR-PTR1 resp-buf-ptr Reply-Update-PTR (SAP list) Indication Reply Buffer Byte 1 resp-buf/data-length resp-status Byte 2 (08h,18h: lowprior 0Ah,1Ah highprior) Net data Buffer of responder Figure 5-8 Structure of the Reply-on-Indication Block The response buffer is included in the 'Reply-On-Indication Blocks' area and contains the response buffer length, the response status, and the net data of the response frame.
  • Page 49 FLC Interface Reply Header Byte 0 resp-data- Here, the FLC enters the length of the response buffer. length Byte 1 resp-status The responder status is entered in this field. The status must be provided by the FLC. The following codes are permitted.
  • Page 50 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 51: Dp Interface

    DP Interface PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 52: Description

    Description Supported Productive Services The SPC 4-2 supports the following productive services of PROFIBUS DP (DIN 19245 part 3, EN 50170 volume 2, IEC 61158, IEC 61784-1) ● Data Exchange ● Read Input Data ● Read Output Data ● Global-Control (Sync, Freeze, Clear-Data) Other DP Services Other PROFIBUS-DP services (diagnostics, parameter assignment, and configuration) must be implemented by the FLC;...
  • Page 53 DP Interface Request frames at a SAP other than the DEFAULT SAP are accepted only if the SSAP is different from the DEFAULT SAP. The request SSAP must have suitable parameters assigned by the FLC. The received data are entered in the indication queue.
  • Page 54 ● either with the "old" input data of reply update buffer D (in other words reply update buffers D and N are not swapped before sending the response). This is the situation when no valid input data have been entered in the reply update buffer N (in other words, RUP-N-Valid = 0 in the DEFAULT SAP) or the input data in reply update buffer D are frozen (DIAG.FREEZE mode = 1, see Section 6.2.4).

  • Page 55: Productive Services

    DP Interface Productive Services 6.2.1 Data Exchange Description The controller for the PROFIBUS DP protocol must be implemented by the FLC. As a DP slave, the SPC 4-2 can only receive request frames from the DEFAULT SAP of the DP master at its own DEFAULT SAP when the DP controller is in the "Data Exchange"...
  • Page 56 Access-Value = 08H filters all request frames except for ● Send and Request Data low (SRD-low), ● Send and Request Data high (SRD-high), ● Send and Request Data with DDB (DDB-Request), ● DDB-Response low, ● DDB-Response high. Since the filter allows DDB-Response-low/high frames to pass, this means that the SPC 4-2 as a DP slave can also listen on the bus using the DEFAULT SAP and evaluate the received data.

  • Page 57: Read-Input-Data

    DP Interface 6.2.2 Read-Input-Data Description Read-Input-Data is an SRD frame without request data from any bus master with SSAP = 62 to SAP 56 of the DP slave. As a DP slave, the SPC 4-2 can only evaluate this frame if the DP controller is in the "Data Exchange" state. In all other states (for example Wait-PRM, Wait-Config), SAP 56 must be deactivated by the FLC with Request-SA = 7FH.

  • Page 58: Read-Output-Data

    6.2.3 Read-Output-Data Description Read-Output-Data is an SRD frame without request data from any bus master with SSAP =62 to SAP 57 of the DP slave. As a DP slave, the SPC 4-2 can only evaluate this frame if the DP controller is in the "Data Exchange" state. In all other states (for example Wait-PRM, Wait-Config), SAP 57 must be deactivated by the FLC with Request-SA = 7FH.

  • Page 59: Global Control (Sync, Freeze, Clear Data)

    DP Interface 6.2.4 Global Control (Sync, Freeze, Clear Data) Description The global control frame is an SDN frame with 2 bytes of net data from the DP master with SSAP = 62 to SAP 58 of the DP slave. As a DP slave, the SPC 4-2 can only evaluate this frame if the DP controller is in the "Data Exchange"...
  • Page 60 Byte 0: Control Command Meaning Meaning Reserved "Reserved" indicates that these bits are reserved for future expansions and must have the value "logical 0". If the bit "Check-GCT-Resbits-Off = 0" is set in mode register 2, the reserved bits are scanned for zero. If at least one of the reserved bits has the value "logical 1", the SPC 4-2 executes "Leave-Master".

  • Page 61: Leave-Master

    DP Interface Byte 1: Group Select Group select decides which groups of DP slaves will be addressed. The bits of the group select byte of a received global control frame are ANDed by the SPC 4-2 with the bits of the "Active-Group-Ident" byte of the DEFAULT SAP. The DP slave is addressed when the AND logic operation returns a value other than zero in at least one position.

  • Page 62: Baudrate Search

    ● The received net data length of a DP data frame is less than the indication buffer length in the DEFAULT SAP: The SPC 4-2 replies with the input data from reply update buffer D, if DIAG.FREEZE mode = 0 and RUP-N-Valid = 1, the reply update buffers D and N are first swapped.

  • Page 63: Asic Interface

    ASIC Interface ASIC Interface PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 64 Overview The following sections describe the registers that specify both the hardware function of the ASIC and the frame processing. Parameters that intervene directly in the controller or semaphores that are set directly by the controller are stored in a parameter latch array on the SPC 4-2. All other parameters are in the lower area of the RAM.

  • Page 65: Latch Parameters

    ASIC Interface Latch Parameters 7.1.1 Slot-Time Register (can be written, modifiable only in offline status): Address Bit Position Meaning Control register TSLOT (Intel) 7..0 Address Bit Position Meaning Control register TSLOT (Intel) 13..8 Table 7-1 : Slot Time Register The wait to receive time TSL is a maximum of 14 bits long and is specified in transmission bit steps.
  • Page 66 The dividing factor for the baud rate generator is set in the baud rate register. The dividing factor G is calculated according to the following formula: − ∗ ABTAST clock in MHz baudrate dividing factor ABTAST is obtained from the FILTER-AN/AUS and SYN/ASYN bits of mode register 0: SYN/ASYN FILTER-...

  • Page 67: Begin-Ptr Register

    ASIC Interface 7.1.3 BEGIN-PTR Register (can be written, modifiable only in offline status): Address Bit Position Meaning Control register BEGIN-PTR 7..0 Table 7-4 : BEGIN-PTR Register The BEGIN-PTR is the address of the first segment of the indication queue. 7.1.4 UMBR-PTR Register (can be written, modifiable only in offline status): Address...

  • Page 68: Trdy Register

    7.1.6 TRDY Register (can be written): Address Bit Position Meaning Control register (Intel) TRDY-Reg 7..0 Table 7-7 : TRDY Register The TRDY time must elapse as an idle time on the bus before a response frame is sent. It is a maximum of 8 bits long and is specified in transmission bit steps. The FLC can change TRDY if the MAC state machine is not in the offline status.

  • Page 69: Syn-Time Register

    ASIC Interface 7.1.8 SYN-Time Register (can be written, modifiable only in offline status): Address Bit Position Meaning Control register TSYN-Reg 7..0 (Intel) Table 7-9 : SYN-Time Register In the asynchronous mode (RS-485), 33 bits must always be set here. In the synchronous mode, the T IFG (interframe GAP time) is set (4...32 bits) 7.1.9 Delay-Timer Register (can be read)

  • Page 70: Factor-Delay-Timer-Clock Register

    7.1.10 Factor-Delay-Timer-Clock Register (can be written): Address Bit Position Meaning Control register TFAKOT 7..0 (Intel) Address Bit Position Meaning Control register TSLOT 13..8 (Intel) Table 7-11 : Factor-Delay-Timer-Clock Register The Factor-Delay-Timer-Clock register determines the dividing factor dependent on the input clock pulse for the delay timer (refer to the section on SPC 4-2 timers). 7.1.11 Mode Register Mode Register 0 Mode-REG0, can be written, modifiable only in offline status): Fixed parameters...
  • Page 71 ASIC Interface Address Bit Position Meaning Control register FILTE EARL INT- XPB/ XRTS SYN/ DIS- Mode-Reg0 R_AN Mode START- ASYN 7..0 /AUS READ CONTRO Bit 0 DIS-START-CONTROL Disable start bit monitoring (hamming distance 4, test in UART) Start bit monitoring is enabled in the receiver (status following reset) Start bit monitoring is disabled in the receiver Bit 1 DP-Mode...
  • Page 72 Mode Register 1 (Can be written, START-SPC 4-2, modifiable only in offline status; EOI, SM-MODE can be modified during operation) Some control bits must, however, be modified continuously during operation. These are put together in a special register (mode register 1) and can be set (Mode_Reg_S) or cleared (Mode_Reg_R) independent of each other.
  • Page 73 ASIC Interface Address Bit Position Meaning Control register Baudra DEL-TIM Mode-Reg1- Mode Reset 7..0 Search Cmd- Baudra DEL-TIM Mode-Reg1- Leav Mode 7..0 Offlin Search Mast Bit 0 START-SPC 4-2 Exit the offline status The SPC 4-2 leaves the online status and changes to passive idle or the SM mode depending on whether the SM mode bit was also set and the idle and syni timers are started.
  • Page 74 Mode Register 2 Mode register 2 of the SPC 4 was extended by three bits (7..5) in the SPC 4-1 and therefore also in the SPC 4-2: Mode register 2 (can only be written) Address Bit Position Meaning Control register SPEC CHECK- CHECK-...
  • Page 75 ASIC Interface Bit 0 XHOLDTOKEN Here, the level of the output pin XHOLDTOKEN can be set. This output exists only to ensure pin compatibility with SPC2. High (reset value) Bit 1 XINTCI Here, the level of the output pin XINTCI can be set. This output exists only to ensure pin compatibility with SPC2.
  • Page 76 Mode Register 3 Mode register 3 (can only be written) Address Bit Position Meaning Control register XHOLDTOKEN Quic Debu Pulse Mode-Reg3 Mode ment modulat 7..0 leve Sync -New PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 77 ASIC Interface Bit 0 Pulse Modulation Pulse modulation for the current-saving link between SPC4-1 or SPC4-2 and the ASIC SIM1 can be activated here. Pulse modulation is deactivated (reset value) Pulse modulation is enabled Bit 1 Debug The SPC4-1 or SPC4-2 triggers an interrupt (write violation) as soon as a previously specified micro sequencer command is executed.
  • Page 78 Mode Register 4 Mode register 4 is new in the SPC 4-2 and contains the following bits: Address Bit Position Meaning Control register Enab Enable-Takt- Start Mode-Reg4 pling Sync _FF- 7..0 mode Send Bit 0 Start-FF-Send Start for sending a frame (only possible in FF mode) Sending deactivated (reset value) The SPC 4-2 starts to send a frame immediately unless it is currently receiving.

  • Page 79: Status Register

    ASIC Interface 7.1.12 Status Register The status register reflects the current SPC 4-2 status and can only be read. Address Bit Position Meaning Control register Enable EARLY IND- IND- Passi Status-Reg Stored LINE (Intel) state 7..0 Receiv READ Idle Stored Address Bit Position Meaning...
  • Page 80 Bit 0 Offline/Passive-Idle Offline-/Passive-Idle state The SPC 4-2 is offline The SPC 4-2 is passive-idle Bit 1 SM-State SM state The SPC 4-2 is not in the SM mode The SPC 4-2 is in the SM mode Bit 2 Passive-Idle Passive-idle state The SPC 4-2 is not in the passive-idle state The SPC 4-2 is in the passive-idle state...
  • Page 81 ASIC Interface Node in SM mode Bit 12, Version Version ID of the SPC 4-2 01 = Version ID in the compatibility mode (as for SPC4-1) 10 = Version ID for SPC 4-2 extended mode Rest Not possible Bit 14, Chip Coding 01 =...

  • Page 82: Fail-Safe Mode

    Fail-safe Mode An additional mode register bit "Spec-Clear-Mode" (bit 5 in mode register 2), enables the fail-safe mode. The fail-safe mode is enabled by setting "Spec-Clear- Mode = 1". The "IND-N-Cleared" and "IND-U-Cleared" bits are added to the access byte of the default SAP: Access byte( 3..0) := Access-Value...
  • Page 83 ASIC Interface If "Spec-Clear-Mode = 1" is set, the SPC 4-2 also accepts data frames without output data in the "Data Exchange" state of the DP controller. This applies regardless of the value of the indication buffer length set in the default SAP of the SPC 4-2.

  • Page 84: Time-Of-Day Synchronization

    Time-of-Day Synchronization The SPC 4-2 supports two time-of-day synchronization mechanisms. The "En- Clock-Sync" parameter bit (bit 6 in mode register 2) selects the required mechanism. If "En-Clock-Sync := 0" is set (status following reset), the SPC 4-2 behaves like the SPC 4 in terms of time-of-day synchronization.

  • Page 85: Ddb Mechanism

    ASIC Interface DDB Mechanism The DDB mechanism is enabled in the PROFIBUS mode (XPB/PA = 0) of the SPC 4-2 with "En-DDB-Mode := 1" (bit 7 in mode register 2). If this bit is not set, all DDB frames are filtered. In the PA mode (XPB/PA = 1) of the SPC 4-2, the DDB mechanism is always enabled, the parameter bit "En-DDB mode"...

  • Page 86: Activating The Extensions

    Activating the Extensions The expansions of the SPC 4-2 are all activated using previously unused parameter registers. The SPC4/SPC4-1 does not evaluate address bits 7 to 5 when the parameter registers are accessed so that all registers can be accessed under several addresses (write and read).

  • Page 87: Memory Expansion To 3 Kbytes

    ASIC Interface Memory Expansion to 3 Kbytes The SPC 4-2 has an extra mode (can be set in mode register 3, see Section 7.1.11), in which the memory segment size of the internal RAM is increased from 8 to 16 bytes. With this mode, access to this RAM using the base pointer can theoretically address up to 4 Kbytes instead of the previous maximum of 2 Kbytes (although only 3 Kbytes are implemented.

  • Page 88: Memory Wastage With 16-Byte Segments

    7.6.1 Memory Wastage with 16-Byte Segments Due to the extra 16-byte segment for the 8-byte long header, each indication block wastes 8 bytes of memory. At the end of the data, in contrast to 8-byte segmentation, it can waste a further 8 bytes. Each Reply-on-Indication block can waste a further 8 bytes at the end.

  • Page 89: Ff Mode

    ASIC Interface FF Mode After activating the FF mode with the FF-Mode bit of mode register 3 (the FF mode is a variant of the PA mode but does not work in the PA mode !), the user must activate the Start-SPC4 bit in mode register 1 as was the case on the SPC4/SPC4- 1.
  • Page 90 If errors occur when the Manchester receiver is receiving, it can no longer reliably detect the end delimiter and therefore the end of the frame. Reception could then go on forever. To prevent this, reception is terminated by the microprogram whenever an error is detected during reception.

  • Page 91: Error Trigger Signal

    ASIC Interface Error Trigger Signal This signal should be used to trigger an oscilloscope if a transmission error occurs. It should be activated either by receive or send errors. A receive error means that the SPC 4-2 receiver detected an error in the bit stream. A send error means that the frame sent by the SPC 4-2 differs from the simultaneously received frame.
  • Page 92 Error counter: The error counter is a new SPC 4-2 16-bit register. It must be read by the host in bytes (high byte address 0x328, low byte address 0x329); in other words, word access is not allowed (no automatic swapping between "high" and "low" byte with Intel or Motorola access).

  • Page 93: Interrupt Controller

    ASIC Interface Interrupt Controller The interrupt controller informs the processor (uP) of indication messages and various error events. Up to 16 events are stored on the interrupt controller and applied to an interrupt output. The controller has no priority level and does not supply an interrupt vector (not 8259A compatible!).

  • Page 94: Interrupt Assignment

    7.9.1 Interrupt Assignment Address Bit Position Meaning Control register Correct Wrong Syni- Del- Rec- Int-Reg (IR) -SD/ Error Tim- Frame 7..0 (Intel) Overru sive State Overflo Output- Watch- Rese Idle Data- Dog- Exchan Reset Address Bit Position Meaning Control register IND-PRE FIFO Rese...
  • Page 95 ASIC Interface Bit 0 MAC_Reset After the SPC 4-2 has processed the current job, it changes to the offline state (by setting 'Go-Offline' or if a fatal error has occurred from SM mode). Bit 1 REC-Frame-Overflow The SPC 4-2 received a new frame although the indication queue was still full or the FIFO in the UART had an overrun due to the processor locking the bus too long.

  • Page 96: Interrupt Assignment In The Ff Mode

    7.9.2 Interrupt Assignment in the FF Mode As soon as the FF mode is activated, the interrupt sources are switched over. The bits are of these 16-bit interrupt register have the following meaning in the FF mode: Address Bit Position Meaning Control register...
  • Page 97 ASIC Interface Bit 0 MAC_Reset Frame sent Bit 1 Rec-Frame Overflow Receive buffer overflow Bit 2 Timer 0 Timer 0 elapsed Bit 3 Timer 1 Timer 1 elapsed Bit 4 Timer 2 Timer 2 elapsed Bit 5 Syni-Error Error receiving frame (CRC or Manchester error) Bit 6 Timer 3 Timer 3 elapsed...

  • Page 98: Clock Synchronization

    7.10 Clock Synchronization Description Clock synchronization is triggered by a global control frame (SD2 to SAP58). The SPC 4-2 handles all global control frames like the SPC 4-1. In addition, however, when the GCT is error-free, it compares the station address contained in the frame with a station address set in the internal RAM (test for valid constant-time scan master).
  • Page 99 ASIC Interface This results in the following: For DP: 3.25 T delay-min Jitter: 0.5 T The use of the digital filter in DP increases the jitter by T spc4 For PA (LE = 6): 17.875 T delay-min Jitter: 2.0 T For PA (LE = 7): 11.875 T delay-min...

  • Page 100: Spc 4-2-Timers

    7.11 SPC 4-2-Timers 7.11.1 Delay Timer Description The delay timer on the SPC 4-2 is implemented as a 24-bit timer. To remain compatible with SPC 4, the delay timer is limited to 16 bits in the PA mode (XPB/PA=1).. It is automatically reset and started when a "first-time frame" is received.

  • Page 101: Idle Timer

    ASIC Interface DEL_CLK Divider for Delay timer FAKT_DEL_CLK Figure 7-25 Delay Timer Function (1) DEL_CLK last bit "first" SM time detected RD1 counter is reset RD1 counter is stopped and read out stop start Delay timer RD1: Receive delay timer If the maximum counter reading is reached, it continues at 0 and an interrupt (Del-Tim-Overrun) is triggered.

  • Page 102: Syni-Timer

    TSYN TSYN:The synchronization time TSYN is the minimum time during which each node must detect the idle state on the transmission medium before it is allowed to accept the start of a call or token frame. In the asynchronous mode, the Syn-Time is 33 bits. In the synchronous mode, the Syn-Time can be selected.

  • Page 103: Slot Timer

    ASIC Interface 7.11.4 Slot Timer Description This timer generates the count intervals for the time-out timer. Load Syni /Slot XSlot/ Syni Slot 1.Slot 2.Slot Figure 7-27 Controlling the Slot Timer The slot timer is a cyclic timer that increments with BRCLK. It is loaded with the idle time at the start.

  • Page 104: New Timers In The Ff Mode

    The timeout timer (9-bit) is a one-shot-timer that increments at the slot interval rate ). The controller takes the XSlot/Syni status bit. If the Syni-timer is running (XSlot/Syni = 1), the timeout timer is locked. With the change from Syni to Slot (XSlot/Syni = 0), the timeout timer is cleared, enabled, and incremented at each TOCLK (slot interval).
  • Page 105 ASIC Interface To start a "one-shot" timer again after it has elapsed, the user simply needs to write a start command to the timer control register again. If you want to retrigger a "one- shot" timer that has not yet elapsed, you must first stop the timer and then start it again.
  • Page 106 Timer-Control Register (address 0x31E; write only): (1:0) Status of Timer0 remains unchanged. Timer0 is restarted at the start value. Timer0 resumes count (only effective if timer was previously stopped). Timer0 is stopped. (3:2) Status of Timer1 remains unchanged. Timer1 is restarted at the start value. Timer1 resumes count (only effective if timer was previously stopped).

  • Page 107: Asynchronous Interface

    Asynchronous Interface PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 108: Baud Rate Generator

    Baud Rate Generator Description The baud rate generator (BRG) provides all the clock rates required on the SPC 4-2 for transmitting data in the asynchronous UART format at the following data rates: 9.60 Kbps 19.20 Kbps 93.75 Kbps 187.50 Kbps 500.00 Kbps 1.50 Mbps 3.00 Mbps...

  • Page 109: Transmitter

    Asynchronous Interface Transmitter Description The transmitter converts the parallel data structure into a serial data stream with a start bit, 8 data bits, an even parity bit and a stop bit. The least-significant data bit is sent first. Request-to-Send (RTS) is generated before the first character. The XCTS input is available for connecting a modem.

  • Page 110: Transmitter

    Transmitter Description The receiver converts the serial data stream into a parallel data structure. It scans the serial data stream at 4 x the transmission rate (at 12 Mbps) or at 16 x the transmission rate. Synchronization of the receiver always begins at the negative- going edge of the start bit.

  • Page 111: Serial Bus Interface Profibus Interface (Asynchronous)

    Asynchronous Interface Serial Bus Interface PROFIBUS Interface (Asynchronous) 8.4.1 Interface Signals Data transmission is in the RS-485 mode (RS-485 physical bus characteristics). The SPC 4-2 must be connected to the electrically isolated interface drivers with the following signals: Signal Names Type Note non Tristate...

  • Page 112: Timing

    Notice: • The names A and B of the lines of the connector comply with the names in the RS-485 standard and not with those of the pin names of the driver ICs. • The wire length from the driver to the connector must be kept as short as possible.

  • Page 113: Suggested Wiring For Rs-485

    Asynchronous Interface 8.4.3 Suggested Wiring for RS-485 B - Ltg. R T S2M 2P5 A - Ltg. 300R EN 1 G N D D river selection 75A LS176D D iff. voltage > 2V EN 2 Shield 680R C aution: P otential isolation to bus P 5 and 2 P5 &...
  • Page 114 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 115: Synchronous Interface

    Synchronous Interface PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 116: Overview

    Overview Description The synchronous interface allows data transmission complying with IEC 61158-2 (voltage mode, 31.25 Kbps). It includes services of the interfaces defined in this standard between the data link layer and physical layer (FDL-Ph Layer Interface), the Ph DIS sublayer(DCE Independent Sublayer) and Ph MDS (Medium- Dependent Sublayer) for wire media and the corresponding MDS-MAU Interface.

  • Page 117: Baud Rate Generator

    Synchronous Interface Baud Rate Generator Description The baud rate generator can generate the data rate 31.25 Kbps. PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 118: Transmitter

    Transmitter Description The transmitter converts the parallel data structure to a serial data stream. Synchronous transmission complying with IEC 1158-2 uses Manchester coding and start and end delimiters. Each frame is preceded by a preamble. The length of the preamble is stored in the PREAMBLE register. The most significant data bit (in contrast to the asynchronous interface) is set first .
  • Page 119 Synchronous Interface Bit boundaries Preamble (1...8 bytes) Start delimiter End-delimiter Figure 9-4 Bit Coding of the Synchronous Interface The transmitter provides various output signals: ● RTS (request to send) ● TxS (transmit signal) ● ADD (add signal). With the combination of TxS and ADD it is extremely easy to implement an adder circuit to control a current control unit as is used in the interface of an intrinsically safe bus node.
  • Page 120 1 N+ N- Figure 9-5 Output Signals of the Synchronous Transmitter PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 121: Receiver

    Synchronous Interface Receiver Description The receive filter is responsible for conditioning the received signal RxS for clock recovery and clock decoding. The Manchester decoder obtains the data from the filtered received signal. The clock recovery function obtains the CLK1 clock from the filtered received signal.

  • Page 122: Pulse Modulation In The Spc 4-2

    Pulse Modulation in the SPC 4-2 The SPC 4-2 has circuits for a direct connection SIM1-optocoupler-SPC 4-2 (PROFIBUS PA attachment) using the current-saving interface of the SIM 1. A separate adapter circuit is no longer necessary. The circuit is designed for a single application: PROFIBUS-PA Operating frequency on SPC 4-2: 2 MHz Baud rate: 31.25 kbauds...

  • Page 123: Pulse Demodulation

    Synchronous Interface Pulse Demodulation Description The permitted pulse widths of the pulse interface are specified in the SIM 1 specification. Here, 2 µs ± 0.5 µs is specified for a short pulse and 5 µs –0.5 µs/+2 µs for a long pulse. For demodulation of the pulses, the SIM1 specification specifies a timing element with a time of 2.9 µs to 3.2 µs (t3, see SIM1 specification).

  • Page 124: Fast Synchronizer In The Manchester Receiver

    Fast Synchronizer in the Manchester Receiver Description Fast synchronization means finding the bit mid point in the preamble of a Manchester frame (PROFIBUS PA). The SPC4 sets this point on the fourth frame edge in the preamble. The SPC 4-2 attempts to identify this point more accurately by determining the duration of the last high and low phase before the fourth edge.

  • Page 125: Clock Pulses

    Clock Pulses PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 126 Clock pulses at QCLK-IN Operating voltage Transmission mode Clock max. = 1/T asynchronous 48 MHz synchronous 40 MHz 3.3 V asynchronous 20 MHz 3.3 V synchronous 16 MHz Clock timing: Distortion of clock signal up to a ratio of :TCLL 40:60 permitted. At a threshold of 1.5 or 3.7V and 0.7 or 1.8V: Figure 10-1 Clock Timing...
  • Page 127 Clock Pulses From a connected quartz, the clock generator generates the internal CLK, from which all the clock signals required on the SPC 4-2 are generated. The base clock rate is provided to other components (for example the processor) via a selectable divider (Pin 3 "0"=:4, "1"=:2 divided clock rate).
  • Page 128 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 129: Processor Interface

    Processor Interface PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 130: Universal Processor Interface

    8-bit microcontrollers whose CPU is based on the 80C51/52 (80C32) line from INTEL, the MOTOROLA HC11 family, and the 8/16-bit microcontroller of the 80C166 family from SIEMENS, X86-compatable processors from Intel and the HC16 and HC916 family from MOTOROLA. A clock divider is also integrated that provides the internal working clock rate divided by 2 or 4 for external use and therefore allows low-cost systems to be implemented.
  • Page 131 8-bit multiplexed bus ADB(7-0), The following can be connected: • Microcontroller families, e.g. INTEL, SIEMENS, PHILIPS ... Address decoder on the SPC 4-2 is activated; CS signal is supplied internally: • The lower address bits A(7-0) are stored in an internal address latch with the ALE signal.
  • Page 132 • 8-bit non-multiplexed bus: DB(7-0); AB(9-0) The following can be connected: • Microcontroller families, e.g. SIEMENS, 80C16x and INTEL X86 Address decoder on the SPC 4-2 is deactivated; CS signal is supplied to the SPC 4-2 (asynchronous • External address decoding is always required...

  • Page 133: Bus Interface Unit (Biu)

    Processor Interface 11.2 Bus Interface Unit (BIU) Description The bus interface unit provides the interface to the microcontroller. It allows the connected microcontroller access to the internal 3-Kbyte dual port RAM. Depending on the connected microcontroller types, the BIU generates the request signals for the dual-port RAM controller from the control signals (ALE with internally generated CS signal or E-clock rate with an externally applied CS signal.

  • Page 134: Dual-Port Ram Controller

    11.3 Dual-Port RAM Controller 11.3.1 Function The internal maximal 3-Kbyte RAM of the SPC 4-2 is a single-port-RAM. Control by an integrated dual-port RAM controller (DPC) , however, allows almost simultaneous access by both ports (bus interface and microsequencer interface MS).

  • Page 135: Access To The Spc 4-2 With Lock Activated

    Processor Interface 11.3.2 Access to the SPC 4-2 with LOCK Activated Description In the dual-port RAM certain areas are modified both by the FLC and by the MS; these are cells in the SAP list. To avoid data conflicts between write and read- modify-write access, the SPC 4-2 has a lock mechanism (see also the hardware description, section 5.1.2).

  • Page 136: Other Pins

    11.4 Other Pins 11.4.1 Test Pins Description All output and I/O pins can be switched to the high-resistance state via a test pin XTEST0. To test the chip with test equipment (not in the target hardware environment!), an additional input (XTEST1) is provided. In conjunction with various other pins, this input allows the manufacturer to test the chip via a test bus.

  • Page 137: Interrupt Timing

    Processor Interface 11.5 Interrupt Timing Interrupts: Parameters Unit Interrupt-inactive time µs 48 periods of the SPC 4-2 clock (at 48 MHz = 1 µs) 1µs XINT Figure 11-1 Interrupt Timing PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 138: Reset Timing

    11.6 Reset Timing Description To allow the SPC 4-2 to be reset correctly, it requires a pulse of at least 100 ns duration. Min 100 ns Reset Figure 11-2 Reset Timing PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 139: Intel /Siemens 8051 (Synchronous) Etc

    8-bit multiplexed bus ADB(7-0), The following can be connected: • Microcontroller families, e.g. INTEL, SIEMENS, PHILIPS ... Address decoder on the SPC 4-2 is activated; CS signal is supplied internally: • The lower address bits A(7-0) are stored in an internal address latch with the ALE signal.

  • Page 140: Timing 80C32

    11.7.2 Timing 80C32 In this mode, all accesses are started by the falling edge at XRD or XWR. Read : Data valid Write: Figure 11-4 Timing 80C32 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 141 Processor Interface Bus Interface Timing Intel Synchronous Min. Max. Unit ALE pulse width Setup time DB before ALE ↓ 5 (8) Hold time DB after ALE ↓ 8 (12) ALE ↓ to XRD ↓ 20 (30) Setup time AB before XRD ↓ 20 (30) XRD ↓...

  • Page 142: Intel X86 (Asynchronous)

    11.8 Intel X86 (asynchronous) 11.8.1 Circuit Diagram In the X86 mode, the X86 bit must be set in mode register 2. If the SPC 4-2 is connected to a 80286 or similar, remember that the processor access words. This means that either a swapper is required that switches the relevant characters from the SPC 4-2 to the corresponding byte position of the 16- bit data bus when data are read or the lower address bit is not connected and the 80286 accesses words and only the lower byte is evaluated as shown in the...

  • Page 143: Timing X86

    8-bit non-multiplexed bus: DB(7-0); AB(9-0) The following can be connected: (asynchronous • Microcontroller families, e.g. SIEMENS, 80C16x and INTEL X86 INTEL) The address decoder is deactivated on the SPC 4-2; CS signal is supplied to the SPC 4-2: • External address decoding is always required •...
  • Page 144 Min. Max. Unit Setup time AB before XRD ↓ and 20 (30) XCS ↓ active Hold time AB after XWR ↑ XCS, XRD ↓ until DB low resistance 18 (27) XCS, XRD ↑ until DB high resistance 18 (27) Access time of XRD ↓ until data valid + 52 (77) SPC 4-2 XCS, XRD ↓...

  • Page 145: Siemens 80C165 (Asynchronous)

    Asynchronous bus; timing with evaluation of the XREADY signal • 8-bit non-multiplexed bus: DB(7-0); AB(9-0) The following can be connected: • Microcontroller families, e.g. SIEMENS, 80C16x and INTEL X86 (asynchronous Address decoder on the SPC 4-2 is deactivated; CS signal is supplied to the SPC 4-2 INTEL) •...

  • Page 146: Timing 80C165

    11.9.2 Timing 80C165 Description This mode is only reached when bit X86 is deleted in mode register 2 (X86 =0). Although the required write access can be made immediately with 80C165 timing, a wait time of 5 T must elapse before further access is possible. All later SPC 4-2 access is then started by a falling edge at ALE.
  • Page 147 Processor Interface Min. Max. Unit ALE pulse width ALE low phase -t 1 SPC 4-2 Setup time AB before ALE ↓ 20 (30) - T SPC 4- XCS ↓ , XRD ↓ to ALE ↓ SPC 4-2 XCS ↓ , XRD ↓ until DB low resistance 18 (27) XCS ↑...

  • Page 148: Timing 68Hc16 (Asynchronous)

    11.10 Timing 68HC16 (asynchronous) 11.10.1 Timing 68HC16 In this mode, all accesses are started by a falling edge at AS. X C S R ead: R /W D ata valid X D TAC K (early) X D TAC K (norm al) W rite: R /W X D TAC K (early, norm al)
  • Page 149 Processor Interface Min. Max. Unit Inactive time AS AS ↓ until AB valid - 20 SPC 4-2 (30) AS ↓ until XCS ↓ - 10 SPC 4-2 (15) AS ↓ until R/W - 10 (15) SPC 4-2 XCS ↓ , R/W ↑ until DB low resistance 18 (27) XCS ↑...

  • Page 150: Motorola 68Hc11 (Synchronous)

    11.11 Motorola 68HC11 (synchronous) 11.11.1 Timing 68HC11 In this mode, access is started by a rising edge at E-clock. The clock rate of the SPC 4-2 (QCLK-IN) must be at least four times higher than that of the E-clock. Note If E-clock = 3 MHz, CLK must be 24 MHz.
  • Page 151 Processor Interface Min. Max. Unit Period E-clock Setup time AB before E-clock ↑ 20 (30) Hold time AB after E-clock ↓ 15 (22) Setup time XCS, R/W E-clock ↑ 15 (22) Hold time XCS, R/W to E-clock ↓ XCS ↓ , R/W ↑ until DB low resistance 18 (27) Access time of E-clock ↑...
  • Page 152 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 153: Technical Specifications

    Technical Specifications PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 154: Maximum Limit Values

    12.1 Maximum Limit Values Parameters Meaning Limits Unit DC supply voltage -0.3 to 7.0 Input voltage -0.3 to VDD +0.3 Output voltage -0.3 to VDD +0.3 DC output current see table DC supply current IDD, ISS Approx. 60 Ambient temperature Topt -40 to +85 °C...

  • Page 155: Permitted Operating Values

    Technical Specifications 12.2 Permitted Operating Values Parameters Meaning MIN. MAX. Unit DC supply voltage (VSS=0V) DC supply voltage (VSS=0V) Input voltage Input voltage (high level) Input voltage (low level) 0.3 VDD Output voltage Ambient temperature °C DC supply current typically 5 V/12 Mbps DC supply current typically...

  • Page 156: Power Consumption

    12.3 Power Consumption The power consumption of a large-scale integrated digital module such as the SPC 4-2 depends to a great extent on the selected mode. The power supply, the external clock frequency, data transmission rate and type and frequency of access to the memory interface determine the current consumption of the chip.

  • Page 157: Dc Specification Of The Pad Cells

    Technical Specifications 12.4 DC Specification of the Pad Cells Parameters NAME MIN. Type MAX. Unit Threshold voltage 0 level Schmitt trigger at 3.3 V Threshold voltage 1 level Schmitt trigger at 3.3 V Threshold voltage 0 level Schmitt trigger at 5.0 V Threshold voltage 1 level Schmitt trigger at 5.0 V Input leakage current...

  • Page 158: Ratings Of The Output Drivers

    12.5 Ratings of the Output Drivers Signal line Direction Driver type Driver Cap. Pullup strength load DB 0-7 Tristate 4 mA 50 pF min. 50 k Ω RTS-ADD Tristate 4 mA 50 pF Tristate 4 mA 50 pF X/INT Tristate 4 mA 50 pF X/INTCI...

  • Page 159: Package

    Package PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 160 A = 12.0 ±0.2 mm B = 10.0 ±0.2 mm C = 10.0 ±0.2 mm D = 12.0 ±0.2 mm F = typ. 1.0 mm G = typ. 1.0 mm H = 0.37 ±0.08 mm J = 0.8 mm L = 0.6 ±0.15 mm M = 0.15 ±0.05 mm (pin thickness) P = 1.4 ±0.15 mm θ...

  • Page 161: Instructions On Handling

    Package 13.1 Instructions on Handling Warning When handling and working with electronic components, make sure that you keep to the ESD guidelines . Warning The SPC 4-2 is a component subject to cracking, and must be handled accordingly. ● Before working on the SPC 4-2 it must be dried if the chip has been stored for more than 48 hours without being in a dry pack.
  • Page 162 ● Lead Finish: Sn-Ag ● During lead-free infrared soldering, the maximum temperature 260 °C must not be exceeded on the package surface and the temperature must not exceed 230 °C for a period longer than 30 to 50 seconds. Figure 13-2 Example of a temperature profile PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 163: Labeling

    Package 13.2 Labeling The labeling of the SPC 4-2 LF contains the following information as shown symbolically Figure 13-3: Manufacturer: Siemens AG Type name: SPC 4-2 LF Type code: company internal code; 190C580EF003 Production information: coded production identifier allowing a batch to be identified if faults are discovered.

  • Page 164: Packaging Of The Asic

    13.3 Packaging of the ASIC The SPC 4-2 ASICs ship in two different types of packaging: ● Small pack (pack of 5) ● Single Tray (pack of 160) This type of packing is suitable for laboratories. Since the positioning is not reproducible, this is not suitable for automatic assembly.
  • Page 165 Package Figure 13-4 Tray Spezification PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 166 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 167: References

    References ● DIN 19245 Part 1 (Beuth-Verlag) ● DIN 19245 Part 2 (Beuth-Verlag) ● DIN E 19245 Part 3 (Beuth-Verlag) ● PNO Guidelines PROFIBUS-PA (PNO) ● EN50170 Volume 2 ● IEC 61158:2000 Part 2, 3, 4, 5, 6 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 168 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 169: Addresses

    Addresses PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 170: Pno

    15.1 PROFIBUS User Organization Head Office Haid- und Neu- Straße 7 76131 Karlsruhe Germany Tel.: (0721) 9658-590 Fax.: (0721) 9658-589 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 171: Contacts In The Interface Center

    Addresses 15.2 Contacts in the Interface Center Siemens AG ComDeC Correspondence to: Postfach 2355 90713 Fürth House address: Würzburgerstr.121 90766 Fürth Tel.: (0911) 750 – 2080 Fax: (0911) 750 – 2100 E-mail: ComDeC@fthw.siemens.de PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 172 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 173: Appendix

    Appendix PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 174: Server Software For The Spc 4-2

    16.1 Server Software for the SPC 4-2 Figure 16-1 and Figure 16-2 show the basic structure. Processor SPC 4 field device e.g. M 377 xx Siemens 80c165 PROFIBUS 80c32 / 8051 Controller Local RAM SIM 1 Local flash Siemens IEC H1...
  • Page 175 Appendix User program PROFIBUS Application Layer Interface PROFIBUS Fieldbus Message Specification PROFIBUS Distributed PROFIBUS Lower Layer Interface SPC 4 Interface Figure 16-2 System Environment of the PROFIBUS PA/FMS/DP Server Software Suitable server software is available from the SIMATIC NET Provider, TMG. PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

  • Page 176: Sim1

    PROFIBUS PA and FF. In conjunction with the SPC 4-2 (the Siemens PROFIBUS controller for slave applications), the functions of a PROFIBUS and FF slave can be handled optimally from the physical attachment to the communication control.
  • Page 177 Appendix The following picture shows one possible way of attaching the SPC 4-2 to the ASIC SIM 1. Transistor Diode sensor SPC 4 SIM 1 bridge actuator Reset Resistor 3.3 V Figure 16-4 Application Example SIM 1 in the constant current mode with SPC 4-2 without electrical isolation PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...
  • Page 178 PROFIBUS Controller SPC 4®-2 LF C79000-G8976-C157-3...

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