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7.11
SPC 4-2-Timers
7.11.1 Delay Timer
Description
The delay timer on the SPC 4-2 is implemented as a 24-bit timer. To remain
compatible with SPC 4, the delay timer is limited to 16 bits in the PA mode
(XPB/PA=1).. It is automatically reset and started when a "first-time frame" is
received. The counter is incremented until it is read. At each overrun, an interrupt
(Del-Tim-Overrun) is generated and incremented.
The counter reading must be reset after it is read out so that no further delay
timer overrun interrupt is generated and so that the system management can
recognize when a second SM-Time frame arrives (for example, if the first SM-Time
frame was lost due to a bus problem), for further details refer to system
management (SM-Time). System management must be capable of handling
possible error situations such as two consecutive second SM-Time frames from
different time masters.
The FAKT_DEL_CLK divider has a range from 64 to 1536.
FAKT
_
Quartz
48 MHz
20 MHz
2 MHz
Table 7-24 : Formula for Calculating FAKT_DEL_CLK
Note
According to PROFIBUS-PA a resolution of 32 µ s should be selected, the
divider FAKT_DEL_CLK must be set depending on the required quartz
frequency.
When selecting the quartz frequency, the table for the baud rate generator must be
taken into account.
100
Quarz
=
DEL
_
CLK
DEL
_
FAKT_DEL_CLK
1535
31.25 kHz
639
31.25 kHz
63
31.25 kHz
−
1
CLK
DEL_CLK
Resolution=1/DEL_CLK
32 µ s
32 µ s
32 µ s
PROFIBUS Controller SPC 4®-2 LF
C79000-G8976-C157-3
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