Siemens SIMATIC NET SPC 4-2 LF Manual page 127

From a connected quartz, the clock generator generates the internal CLK, from
which all the clock signals required on the SPC 4-2 are generated. The base clock
rate is provided to other components (for example the processor) via a selectable
divider (Pin 3 "0"=:4, "1"=:2 divided clock rate).
With the HC11 Motorola family, the E-clock must only be ¼ of the input clock rate
of the SPC 4-2 (Osc.)
(1MHz,24MHz)
Figure 10-3 Overview of the Connection Scheme for INTEL and Motorola CPUs with
PROFIBUS Controller SPC 4®-2 LF
C79000-G8976-C157-3
Synchronous bus clock between CPU and SPC
INTEL CPU
:2 (internal)
BIU
Divider
RAM
ISCLK-Out 2
CLK
(2MHz,48MHz)
Synchronous Bus Timing
Motorola CPU
(2MHz,48MHz)
:4 (internal)
(500kHz,12MHz)
BIU
Divider
2
CLK
(2MHz,48MHz)
Clock Pulses
E-clock
RAM
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