Siemens SIMATIC NET SPC 4-2 LF Manual page 131

TYPE and MODE
TYPE , MODE
MOTOROLA microcontroller with the following characteristics:
•
•
The following can be connected:
•
•
All other HC11 types with a multiplex bus must select the addresses A(7-0) externally from
the data D(7-0).
The address decoder is deactivated on the SPC 4-2; CS signal is supplied to the SPC 4-2:
•
1 1
•
(synchronous
Condition:
Motorola)
SPC 4-2 clock (QCLK-IN) must be at least four times higher than the required bus clock
rate (E-clock rate).
MOTOROLA microcontroller with the following characteristics:
•
•
1 0
The following can be connected:
•
(asynchronous
Address decoder on the SPC 4-2 is deactivated; CS signal is supplied to the SPC 4-2:
Motorola)
The chip-select signal exists on all microcontrollers and can be programmed.
INTEL, CPU Basis 80C51/2 (80C32), microcontrollers from various vendors
•
•
The following can be connected:
•
Address decoder on the SPC 4-2 is activated; CS signal is supplied internally:
0 1
•
•
•
Wiring: Connection diagrams are stipulated by the specification.
(synchronous
INTEL)
PROFIBUS Controller SPC 4®-2 LF
C79000-G8976-C157-3
The SPC 4-2 interface supports the following microcontroller
Synchronous (rigid) bus; timing without evaluation of the READY signal
8-bit non-multiplexed bus: DB(7-0), AB(9-0)
HC11 types: K, N, M and F1
HC16 and HC916 types with programmable ECLK timing
On microcontrollers with chip-select logic: K, F1, HC16, HC916 are the chip-select
signals that can be programmed in terms of address range, priority, polarity and the
window width in the write or read cycle.
On microcontrollers without chip-select logic; N, M and others require an external chip-
select logic. This means additional hardware investment and fixed assignments.
Asynchronous bus; timing with evaluation of the READY signal
8-bit non-multiplexed bus: DB(7-0); AB(9-0)
HC16 and HC916 types
Synchronous (rigid) bus; timing without evaluation of the READY signal
8-bit multiplexed bus ADB(7-0),
Microcontroller families, e.g. INTEL, SIEMENS, PHILIPS ...
The lower address bits A(7-0) are stored in an internal address latch with the ALE
signal. On the SPC 4-2 , the internal CS decoder is activated and generates its own CS
signal from the address A(9- 0).
The integrated address decoder is hardwired so that the SPC 4-2 must always be
addressed at the fixed address at A(7...0)=0000 00xxb , and the SPC 4-2 selects the
corresponding address window from the signals A(1,0) .
In this mode, the CS pin (XCS) must be connected to VDD (high potential)
•
ADB(7-0) to SPC 4-2 pin DB(7-0), AB(15-8) to SPC 4-2 pin
•
AB(7-0) and SPC 4-2 pin AB (9,8) connected to VSS.
•
SPC 4-2 clock (QCLK-IN) must be at least four times higher than the required bus
clock rate.
Processor Interface
131