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7.9
Interrupt Controller
The interrupt controller informs the processor (uP) of indication messages and
various error events. Up to 16 events are stored on the interrupt controller and
applied to an interrupt output. The controller has no priority level and does not
supply an interrupt vector (not 8259A compatible!).
It consists of an interrupt request register (IRR), interrupt mask register (IMR),
interrupt register (IR) and interrupt acknowledge register (IAR).
SPC4
uP
Figure 7-20
Every event is stored in the IRR. Individual events can be suppressed using the
IMR. The entry in the IRR does not depend on the interrupt mask. The event
signals that are not masked in the IMR generate the X/INT interrupt over a
common network. When debugging, the user can set every event in the IRR.
Every interrupt event processed by the processor must be deleted using the IAR by
writing logical '1' to the corresponding bit position. If there is a new event and
acknowledge pending in the IRR at the same time, the event remains stored. If the
processor then enables a mask, make sure that there is no entry from the past in
the IRR. To be on the safe side, the position in the IRR should be deleted before
the mask is enabled.
Before exiting the interrupt routine, the processor must set the "End of Interrupt
Signal (EOI) in mode register 1. This edge change switches the interrupt line
inactive. If an event is still stored, the interrupt output only becomes active following
an interrupt inactivity time of at least 48 clock periods (in other words, at 48 MHz =
1 usec). This makes it possible to return to the interrupt routine when using an
edge-triggered interrupt input.
The polarity of the interrupt output can be set with the INT_Pol mode bit. After the
hardware reset, the output is low active.
PROFIBUS Controller SPC 4®-2 LF
C79000-G8976-C157-3
uP
uP
uP
IR
S
IRR
IMR
R
IAR
uP
Interrupt Controller
SEP_INT
S
FF
R
INT_Pol
ASIC Interface
X/INT
uP
93
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