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7.1.8
SYN-Time Register
(can be written, modifiable only in offline status):
Address
Control
register
317
H
(Intel)
Table 7-9 : SYN-Time Register
In the asynchronous mode (RS-485), 33 bits must always be set here.
In the synchronous mode, the T IFG (interframe GAP time) is set (4...32 bits)
7.1.9
Delay-Timer Register
(can be read)
Address
Control
register
306
H
(Intel)
Address
Control
register
307
H
(Intel)
Table 7-10 : Faktor-Delay-Timer-Clock-Reg
The Delay-Timer Register register contains the current counter reading of the delay
timer.
PROFIBUS Controller SPC 4®-2 LF
C79000-G8976-C157-3
Bit Position
7
6
5
4
TS
TS
YN
YN
5
4
Bit Position
7
6
5
4
TD
TD
TD
TD
EL
EL
EL
EL
7
6
5
4
Bit Position
15
14
13
12
TD
TD
TD
TD
EL
EL
EL
EL
15
14
13
12
3
2
1
0
TS
TS
TS
TS
YN
YN
YN
YN
3
2
1
0
3
2
1
0
TD
TD
TD
TD
EL
EL
EL
EL
3
2
1
0
11
10
7
8
TD
TD
TD
TD
EL
EL
EL
EL
11
10
9
8
ASIC Interface
Meaning
TSYN-Reg
7..0
Meaning
DELAY
7..0
Meaning
DELAY
15..8
69
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