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Figure 7-25
DEL_CLK
stop
RD1
start
Delay
timer
RD1: Receive delay timer
If the maximum counter reading is reached, it continues at 0 and an interrupt
(Del-Tim-Overrun) is triggered.
Figure 7-26
7.11.2 Idle Timer
Description
This timer controls the idle phase directly on the internal bus line RxD/RxA (logical
'1'). Depending on the frame type, the following times must be monitored:
PROFIBUS Controller SPC 4®-2 LF
C79000-G8976-C157-3
CLK
Divider for
FAKT_DEL_CLK
Delay Timer Function (1)
last bit "first" SM time detected
x
0
1
Delay Timer Function (2)
DEL_CLK
Delay
timer
RD1 counter is stopped
and read out
y
y+1
ASIC Interface
RD1 counter is reset
y+n
0
101
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