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t 1
ALE pulse width
t 2
ALE low phase
t 3
Setup time AB before ALE ↓
t 4
XCS ↓ , XRD ↓ to ALE ↓
t 5
XCS ↓ , XRD ↓ until DB low resistance
t 6
XCS ↑ , XRD ↑ until DB high resistance
t 7
Access time of ALE ↓ until data valid
ALE ↓ until XREADY ↓ (early):
t 8
XRD ↑ , XCS ↑ , ALE ↑ until XREADY ↑
t 9
(early, normal)
ALE ↓ until XREADY ↓ (normal)
t 10
t 11
Pulse width XWR
t 12
Hold time XCS after XWR ↑
t 13
Setup time DB before XWR ↑
t 14
Hold time DB after XWR ↑
Hold time AB after XWR ↑
t 15
t 16
XWR ↓ after ALE ↓
t 17
XWR ↑ , XCS ↑ , ALE ↑ until XREADY
(early, normal)
t 18
ALE ↓ until XREADY ↓ (early, normal)
Table 11-11: Bus Interface Timing Intel Asynchronous (80C165)
Times in brackets apply for 3.3 V operating voltage. For write timing, note the
information in Section 11.3.
PROFIBUS Controller SPC 4®-2 LF
C79000-G8976-C157-3
Processor Interface
Min.
Max.
10
5 T
-t 1
SPC 4-2
20 (30) - T
SPC 4-
2
T
SPC 4-2
18 (27)
18 (27)
2 T
SPC 4-2
52 (77)
T
+ 4 (6)
2 T
SPC 4-2
SPC 4-2
18 (27)
17 (26)
2 T
+ 4
3 T
SPC 4-2
SPC 4-2
(6)
18 (27)
10
0
10 (15)
10 (15)
0
T
SPC 4-2
0
16 (24)
T
2 T
SPC 4-2
SPC 4-2
Unit
ns
ns
ns
ns
ns
ns
+
ns
+
ns
ns
+
ns
ns
ns
ns
ns
ns
ns
ns
ns
147
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