Siemens SIMATIC NET SPC 4-2 LF Manual page 141

Bus Interface Timing Intel Synchronous
t 1 ALE pulse width
t 2 Setup time DB before ALE ↓
t 3 Hold time DB after ALE ↓
t 4 ALE ↓ to XRD ↓
t 5 Setup time AB before XRD ↓
t 6 XRD ↓ until DB low resistance
t 7 Access time of XRD ↓ until DB valid
XRD ↑ until DB high resistance
t 8
t 9 XWR pulse width
t 10 Hold time AB compared with XWR ↑
t 11 AB to XWR ↑
Setup time DB before XWR ↑
t 12
t 13 Hold time DB after XWR ↑
Table 11-5: Bus Interface Timing Intel Synchronous
Times in brackets apply for 3.3 V. For write timing, note the information in
Section 11.3.
PROFIBUS Controller SPC 4®-2 LF
C79000-G8976-C157-3
Processor Interface
Min. Max.
10
5 (8)
8 (12)
20 (30)
20 (30)
18 (27)
T SPC 4-2 + 52
(77)
18 (27)
10
0
20 (30)
10 (15)
5 (8)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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