Initial Reset - Epson S1C88655 Technical Manual

5 INITIAL RESET

5 INITIAL RESET
An initial reset must be applied to the S1C88655 to initialize the internal circuits. This chapter
describes the internal initial reset circuits and default values of the CPU registers.
5.1 Configuration of
Initial Reset Circuit
The S1C88655 handles two internal reset signals for
system reset and CPU reset.
System reset
The system reset signal initializes all the I/O
registers and counters. When a system reset is
issued, the CPU reset is issued simultaneously
also.
The following lists the causes of system reset:
(1) External initial reset via the RESET terminal
(2) Internal initial reset by the reset voltage
detector (mask option)
CPU reset
The CPU reset signal resets only the CPU with
the I/O register values maintained.
The cause of CPU reset is as follows:
(1) Internal initial reset by the watchdog timer
overflow signal (mask option)
OSC1
OSC1
oscillation circuit
OSC2
OSC3
OSC3
oscillation circuit
OSC4
Mask option
RESET
Reset voltage
detector
32
___________
Watchdog timer reset
f
OSC1
Divider
f
OSC1
f
OSC3
Divider
f
OSC3
V
DD
V
DD
Mask option
Fig. 5.1.1 Configuration of initial reset circuit
Figure 5.1.1 shows the configuration of the initial
reset circuit.
The CPU and peripheral circuits enter an reset
status when a cause of initial reset occurs. When the
cause of the reset is canceled, the CPU starts reset
exception processing. (See the "S1C88 Core CPU
Manual".)
When this occurs, the reset exception processing
vector, Bank 0, 000000H–000001H from the
program memory is read out and the program
(initialization routine) which begins at the readout
address is executed.
____________
5.1.1 RESET terminal
Initial reset can be done by externally inputting a
LOW level to the RESET terminal.
Be sure to maintain the RESET terminal at LOW
level for the regulation time after the power on to
assure the initial reset. (See Chapter 19, "Electrical
Characteristics".)
In addition, be sure to use the RESET terminal for
the first initial reset after the power is turned on.
However, it is not necessary to reset the IC using
___________
the RESET terminal when the internal reset circuit
is enabled by mask option.
_________
The RESET terminal is equipped with a pull-up
resistor. You can select whether or not to use by
mask option.
Input port pull-up resistor
_________
RESET ............
Watchdog timer
overflow signal
Watchdog timer
/256
CPU-reset-
release clock
/1024
Operating clock status
Reset pulse
delay circuit
A
EPSON
_________
_________
_________
With resistor Gate direct
Mask
option
R Q
S
S1C88655 TECHNICAL MANUAL
NMI
CPU reset
System reset