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Interrupt factor flag
Interrupt enable register
Interrupt priority register
FP27
P27
EP27
FP26
P26
EP26
FP25
P25
EP25
FP24
P24
EP24
Port
FP23
P23
EP23
FP22
P22
EP22
FP21
P21
EP21
FP20
P20
EP20
FTU0
Underflow
Program-
ETU0
mable
FTC0
Compare
timer 0
ETC0
match
FTU1
Underflow
Program-
ETU1
mable
FTC1
Compare
timer 1
ETC1
match
FTU2
Underflow
ETU2
Program-
mable
FTC2
Compare
timer 2
ETC2
match
FTU3
Underflow
Program-
ETU3
mable
FTC3
Compare
timer 3
ETC3
match
FTU4
Underflow
Program-
ETU4
mable
FTC4
Compare
timer 4
ETC4
match
FTU5
Underflow
ETU5
Program-
mable
FTC5
Compare
timer 5
ETC5
match
FTU6
Underflow
Program-
ETU6
mable
FTC6
Compare
timer 6
ETC6
match
FTU7
Underflow
Program-
ETU7
mable
FTC7
Compare
timer 7
ETC7
match
FSERR0
Error
ESERR0
Serial
FSREC0
Receive
interface 0
ESREC0
FSTRA0
Transmit
ESTRA0
FSERR1
Error
ESERR1
Serial
FSREC1
Receive
interface 1
ESREC1
FSTRA1
Transmit
ESTRA1
FTM32
32 Hz
ETM32
FTM8
8 Hz
ETM8
Clock timer
FTM2
2 Hz
ETM2
FTM1
1 Hz
ETM1
S1C88655 TECHNICAL MANUAL
Interrupt vector address generation circuit
Fig. 7.1 Configuration of interrupt circuit
EPSON
7 INTERRUPT AND STANDBY STATUS
PP20
PP21
PPT0
PPT1
PPT2
PPT3
Interrupt priority
level judgment
circuit
PPT4
PPT5
PPT6
PPT7
PSIF00
PSIF01
PSIF10
PSIF11
PTM0
PTM1
Vector
address
IRQ3
IRQ2
IRQ1
45
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