Epson S1C88655 Technical Manual page 47

T1
CLK
A0–A19
CE0
CE1
WR
RD
D0–D7
S1C88655 TECHNICAL MANUAL
T1 T2
CLK
A0–A19
Address
CE0
CE1
WR
RD
D0–D7
Read data
Read cycle
Fig. 6.4.1 Memory read/write cycle (no wait state)
WAIT (4 states inserted)
T2 T3 Tw1 Tw2 Tw1
Address
Read data
Read cycle
Fig. 6.4.2 Memory read/write cycle (with wait state)
6 SYSTEM CONTROLLER AND BUS CONTROL
T3 T4 T1 T2 T3
Address
Write data
Write cycle
Tw2 T4 T1 T2 T3
EPSON
T4
WAIT (4 states inserted)
Tw1 Tw2 Tw1 Tw2 T4
Address
Write data
Write cycle
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