Details Of Control Registers - Epson S1C88655 Technical Manual

6.7 Details of Control Registers

Table 6.7.1 shows the control bits for the system controller.
Address Bit Name
00FF00 D7 BUSMOD
Bus mode
(MCU) D6 CPUMOD CPU mode
D5 –
–
D4 – –
D3 CE3
CE3 (R33)
D2 CE2 CE2 (R32)
D1 CE1
CE1 (R31)
D0 CE0 CE0 (R30)
00FF00 D7 BUSMOD
Bus mode
(MPU) D6 CPUMOD CPU mode
D5 –
–
D4 – –
D3 CE3
CE3 (R33)
D2 CE2 CE2 (R32)
D1 CE1
CE1 (R31)
D0 CE0 CE0 (R30)
00FF01 D7 SPP7
Stack pointer page address
D6 SPP6
D5 SPP5
< SP page allocatable address >
D4 SPP4 • Single chip mode:
D3 SPP3
• Expansion mode:
D2 SPP2
D1 SPP1
D0 SPP0
00FF02 D7 EBR
Bus release enable register
(P24 and P25 terminal specification)
D6 WT2
Wait control register
D5 WT1
D4 WT0
D3 – –
D2 CLKCHG
CPU operating clock switch
D1 SOSC3 OSC3 oscillation On/Off control
D0 SOSC1
OSC1 oscillation On/Off control
∗1 CLKCHG cannot be set to "0" when SOSC1 = "0" (OSC1 oscillation is OFF) and cannot be set to "1" when SOSC3 = "0"
(OSC3 oscillation is OFF).
∗2 Cannot be turned OFF when the CPU is running with the OSC3 clock.
∗3 Cannot be turned OFF when the CPU is running with the OSC1 clock or the watchdog timer is enabled.
Note: All the interrupts including NMI are disabled, until you write the optional value into both the "00FF00H" and
"00FF01H" addresses.
S1C88655 TECHNICAL MANUAL
Table 6.7.1 System controller control bits
Function
CE signal output Enable/Disable
Enable: CE signal output
Disable: DC (R3x) output
CE signal output Enable/Disable
Enable: CE signal output
Disable: DC (R3x) output
only 0 page
0–27H page
WT2 WT1 WT0
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
____
6 SYSTEM CONTROLLER AND BUS CONTROL
1
Expansion Single chip
Maximum Minimum
–
–
CE3 enable CE3 disable
CE2 enable CE2 disable
CE1 enable CE1 disable
CE0 enable CE0 disable
Expansion
Maximum Minimum
–
–
CE3 enable CE3 disable
CE2 enable CE2 disable
CE1 enable CE1 disable
CE0 enable
(MSB)
1
1
1
1
1
1
1
(LSB)
1
P24
BREQ
P25
BACK
Number
of state
14
12
10
8
6
4
2
No wait
–
OSC3 OSC1
On
On
EPSON
0 SR R/W Comment
0 R/W
0 R/W
– –
– Constantly "0" when
– –
– being read
0 R/W
In Single chip mode,
0 R/W
these setting are fixed
0 R/W
at DC output.
0 R/W
1 R
– Expansion mode only
0 R/W
– –
– Constantly "0" when
– –
– being read
0 R/W
0 R/W
0 R/W
1 R
–
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
–
–
0 R/W
0 R/W
0 R/W
– –
– "0" when being read
∗1
1 R/W
∗2
1 R/W
Off
∗3
1 R/W
Off
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