Limitations And Hardware Configuration For Sram A19 (Just For The Test); Table 46. Configuration For Sram A0-A5, A10-11 Addresses, And Command - ST STM32H7B3I-EVAL User Manual

Hardware modifications are listed in
Pin name
PF0
PF1
PF2
PF3
PG0
PG1
PF4
PF5
PG10
1. The default setting is in bold.
2. Remove to avoid stub if necessary.
3. PG10 signal is supplied by VDDMMC. Make sure to supply 3.3 V on VDDMMC (Refer to
Note: If using SD card 1 (Default configuration), use FMC_NE3 = PG10, then SD card 2 cannot be used). If using SD
card 2, use FMC_NE3 = PC8 by fitting JP12 [2-3], then SD card 1 cannot be used.
8.1.4

Limitations and hardware configuration for SRAM A19 (Just for the test)

Limitations with primary functions: Wi‑Fi
Limitations with secondary functions: SAI1 and TRACE cannot be used.
UM2662 - Rev 1
Table 46
Table 46. Configuration for SRAM A0-A5, A10-11 addresses, and command
Signal name
FMC_A0
OCSPI2_IO0
FMC_A1
OCSPI2_IO1
FMC_A2
OCSPI2_IO2
FMC_A3
OCSPI2_IO3
FMC_A10
OCSPI2_IO4
FMC_A11
OCSPI2_IO5
FMC_A4
OCSPI2_CLK
FMC_A5
OCSPI2_NCLK
FMC_NE3
SDIO2_D1
OCSPI2_IO6
DCMI_D2
®
SPI.
below:
Setting
R339
R98
R335
R89
R331
R82
R74
R75
R73
R76
R333
R77
R66
R319
R65
R318
(3) R280 / JP2
R280 / JP2
R115
(3) R118
UM2662
SRAM
(1)
SRAM
ON
(2)
OFF
ON
OFF (2)
ON
OFF (2)
ON
(2)
OFF
ON
(2)
OFF
ON
(2)
OFF
ON
(2)
OFF
ON
(2)
OFF
ON / [1-2]
(2)
OFF / OFF
(2)
OFF
(2)
OFF
Section 6.3.5 )
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