Technical Description; Receiver Architecture - FALCOM JP7-T Series Hardware Description

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GPS-RECEIVER JP7-T

6 Technical Description

6.1 Receiver Architecture

The JP7-T family OEM GPS receiver from FALCOM is new OEM GPS
receiver product that features the SiRFstarII-Low Power chipset. This
completes 12 channel, WAAS-enabled GPS receiver provides a vastly
superior position accuracy performance in a much smaller package. The
SiRFstarII architecture builds on the high-performance SiRFstarI core,
adding an acquisition accelerator, differential GPS processor, multipath
mitigation hardware and satellite-tracking engine. The JP7-T family delivers
major advancements in GPS performance, accuracy, integration, computing
power and flexibility.
Figure 3:
Figure 3 above shows the block diagram of the JP7-T family architecture.
This confidential document is the property of FALCOM GmbH and may not be copied or circulated without permission.
Receiver architecture of the JP7-T family GPS receiver.
VERSION 1.02
Page 19

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