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External Clock Drive
Waveforms
0945G–09/01
Figure 79. External RAM Timing
System Clock Ø
ALE
Address [15..8]
Prev. Address
Data / Address [7..0]
Prev. Address
WR
Data / Address [7..0]
Prev. Address
RD
Note: Clock cycle T3 is only present when external SRAM Wait State is enabled.
Figure 80. External Clock Drive Waveforms
VIH1
VIL1
Table 49. External Clock Drive
Symbol
Parameter
1/t
Oscillator Frequency
CLCL
t
Clock Period
CLCL
t
High Time
CHCX
t
Low Time
CLCX
t
Rise Time
CLCH
t
Fall Time
CHCL
Note:
See "External Data Memory Timing" on page 115. for a description of how the duty cycle
influences the timing for the external data memory.
T1
T2
0
1
4
7
2
13
Address
3a
6
3b
Address
5
10
8
V
= 2.7V to 3.6V
CC
0.0
4.0
250.0
100.0
100.0
1.6
1.6
ATmega103(L)
T3
T4
Address
15
Data
16
11
Data
9
12
V
= 4.0V to 5.5V
CC
0.0
6.0
167.0
67.0
67.0
0.5
0.5
Addr.
14
Addr.
Units
MHz
ns
ns
ns
µs
µs
117
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