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Atmel AT91CAP7A User Manual
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Atmel AT91CAP7A User Manual

Atmel AT91CAP7A User Manual

Starter kit
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AT91CAP7A Starter Kit
....................................................................................................................
User Guide
8559A–CAP–09/08

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Summary of Contents for Atmel AT91CAP7A

  • Page 1 AT91CAP7A Starter Kit ........................User Guide 8559A–CAP–09/08...

  • Page 2: Table Of Contents

    Table of Contents Section 1 Introduction......................... 1-1 Purpose..........................1-1 ™ Starter Kit Board ..................... 1-1 CAP Starter Kit Development Tools................... 1-2 Related Documents ......................1-2 1.4.1 Standards ......................1-2 1.4.2 Reference Documents ..................1-2 Glossary..........................1-3 Section 2 Requirements ......................2-1 General Description ......................
  • Page 3 Switches..........................3-3 Section 4 AT91CAP9-STK Schematics ..................4-1 This section contains the following appended schematics..........4-1 Section 5 Revision History......................5-1 Revisioin Hisory ......................... 5-1 1-ii AT91CAP9-STK Starter Kit User Guide 6351B–CAP–27-Jun-08...

  • Page 4: Section 1 Introduction

    FPGA provides 8256 four-input Lookup Table (LUT) equivalents, corresponding to approximately 84000 gates in the AT91CAP7 MP Block. Headers providing 120 general-purpose I/O connections from the AT91CAP7A, and from the FPGA, for application-specific external interfaces JTAG interface for AT91CAP7 JTAG programming, and a USB-Blaster-JTAG interface for Cyclone 2 JTAG programming.

  • Page 5: Glossary

    Introduction AT91CAP7A Starter Kit Development Tools The AT91CAP7A Starter Kit was designed with the goal of allowing user to get started immediately with no additional software development tool cost. ™ A free evaluation version IAR Systems software compiler and debugger tool is available at: www.iar.com.

  • Page 6: Section 2 Requirements

    Requirements General Description The AT91CAP7A-STK’s objective is to provide a rapid evaluation of the AT91CAP7A product and its derivatives. It does not allow a full emulation of a customized version of the AT91CAP7, but is intended to familiarize the user with the customization concept and architecture of the AT91CAP7.
  • Page 7 Requirements Figure 2-1. AT91CAP7A-STK Interface and Function Overview 40 Pin Header TP’s 3.3V IO Power (EI9) LP3872 (F7) Nand 1.2V Core Power Addr./Data/Cntl Power Jack 5VDC LP3872 Flash 2.1mm. (F7) 2Gbit 10.2V LCD Display Power SDRAM LP3872 Addr./Data/Cntl 64MB (F7)

  • Page 8: External Interfaces

    Positive differential port A 3.3V 4, 5, 6 Electrical 2.3.4 EI4: 1/4 VGA LCD Panel The AT91CAP7A-STK board implements 2 LCD Panel connectors to support 2.8’ and 3.5” LCD panels. Table 2-4. 2.8” / 39-pin ZIF Connector Pinout Signal Name Description Type Level VCC_33 3.3V power supply...
  • Page 9 Cathode 1of LED backlight BACKLIGHT_2_8 Anode of LED backlight 5.0V Upper terminal of touch 3.3V panel left terminal of touch panel 3.3V Bottom terminal of touch TSCREEN_AD 3.3V panel Right terminal of touch MPIO89 3.3V panel AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 10 Red data 3 3.3V MPIO12 Red data 4 3.3V MPIO13 Red data 5 3.3V MPIO14 Red data 6 3.3V MPIO15 Red data 7 3.3V MPIO1 Hsync 3.3V MPIO2 Vsync 3.3V MPIO0 Dot Data Clock 3.3V AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 11 3.3V MPIO7 Data Enable Input 3.3V 2.3.5 EI5: Analog Inputs The AT91CAP7A-STK board implements a 3.81mm-pitch Phoenix MKDS 6-pin terminal block. This con- nector receives four analog inputs. Table 2-6. MKDS 6-pin Terminal Block Pinout Signal Name Description Type Level...

  • Page 12: Ei11: Jtag And Serial Configuration Interfaces

    Table 2-8. HE10 2x5-pin Connector Pinout Signal Name Description Type Level Test Clock 3.3V Test Data Out 3.3V Test Mode Select 3.3V Test Data In 3.3V 4, 6 VCC_33 3.3V power supply 3.3V 7, 8 2, 10 Electrical ground AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...

  • Page 13: Ei13: 64-Lead Extension Connector For The At91Cap9 I/O Lines

    Requirements 2.3.7 EI7: 40-lead Extension Connector for the AT91CAP7A I/O Lines A straight male, 2.54 mm-pitch, 40-pin connector is available on the board as a AT91CAP7 extension connector. Table 2-9. 40-pin Connector Pinout Signal Name Level Signal Name Level MPIO0 3.3V...
  • Page 14 MPIO18 3.3V MPIO89 3.3V MPIO19 3.3V EI13: 40-lead Extension Connector for the AT91CAP7A and FPGA I/O Lines A straight male, 2.54 mm-pitch, 40-pin connector is available on the board as a AT91CAP7 extension connector. AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 15 3.3V PA30 3.3V PA12_CAP7_SPI_C 3.3V PA31 3.3V PA13 3.3V CAP7_RESETn 3.3V PA14_FLASH_CEz 3.3V FPGA_RESETn 3.3V PA15 3.3V FPGA_TST1 3.3V PA16 3.3V FPGA_TST2 3.3V PA17 3.3V FPGA_TST3 3.3V PA18 3.3V FPGA_TST4 3.3V PA19 3.3V 2-10 AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 16 Requirements 2.3.9 EI9: 40-lead Extension Connector for the AT91CAP7A I/O Lines A straight male, 2.54 mm-pitch, 40-pin connector is available on the board as a AT91CAP7 extension connector. Table 2-12. 40-pin Connector Pinout Signal Name Level Signal Name Level EBI_D0 3.3V...

  • Page 17: Characteristics

    ADVREF ADVREF 3.3V 2.4.1.1.2 AT91CAP7A Clocks The internal clocks of the AT91CAP7A are generated by two external quartz sources: 12 Mhz quartz for the MAINCK internal clock 32,768 kHz quartz for the SLCK internal slow clock 2.4.1.2 F2: Altera FPGA 2.4.1.2.1 FPGA Characteristics...
  • Page 18 Refer to the schematic section for implementation details. 2.4.1.5 F5: LCD Panel The AT91CAP7A-STK is delivered with one of 2 different LCD configurations Microtips Technology MTF-TQ28NP741-LB 2.8” TFT LCD, 240RGBx320 dots, displaying 262K colors Microtips Technology MTF-TQ35SP741-AV 3.5” TFT LCD, 320RGBx240 dots, displaying 16.7M colors Refer to the schematic section for implementation details.
  • Page 19 The CAP7_RESETn line is connected to the nRST pin of the AT91CAP7 device. Just how the AT91CAP7A responds to level transitions on the nRST pin is dependent on several user iinterface soft- ware conditions. By default, the AT91CAP7A does not repond to transition on it’s nRST pin, unless the URSTEN bit has previously been set.

  • Page 20: Physical Characteristics

    An ARM-standard 20pin box header (J4) is the connection point for a standard JTAG-ICE tool. When used in conjuction with a software debugger, users can target and execute program code from the AT91CAP7A’s internal 160KB of SRAM. By connecting an Altera Byte Blaster probe to the JTAG box header (J16), users program the EPCS4 FPGA serial configuration device with their desired FPGA functions.

  • Page 21: Board Strap And Switch Configuration

    BACK_LIGHT_3_5, 10.2V, 3.5” LCD Back Light Supply On 3.5” LCD Back Light Supply Off PA1_TX_DATA_DEBUG, AT91CAP7 Debug Unit Connected Debug Unit TX disconnected to RS232 XCVR PA0_RX_DATA_DEBUG, AT91CAP7 Debug Unit Connected Debug Unit RX disconnected to RS232 XCVR AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...

  • Page 22: Connectors 1X3

    LED’ s DS7 - DS0: These LED’s are wired to the FPGA for general purpose use. They can interface the AT91CAP7 PIO as well if a wire net is introduced into the FPGA design configuration, which connects the desired endpoints. LED DS8: Turns green when the FPGA has successfully completed configuration. AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 23 This section contains the following appended schematic Cover Sheet AT91CAP7 I/F AT91CAP7 PIO Memory FPGA IO LED’s / Push Buttons LCD Display USB/Serial/Data Flash Analog Sensors and Buffers AT91CAP7 Power Altera FPGA Power Altera FPGA Programming Power and Reset AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 24 AT91CAP7A-STK Schematics Figure 4-1. Cover Sheet AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 25 AT91CAP7A-STK Schematics Figure 4-2. AT91CAP7 I/F AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 26 AT91CAP7A-STK Schematics Figure 4-3. AT91CAP7 PIO AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 27 AT91CAP7A-STK Schematics Figure 4-4. Memory AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 28 AT91CAP7A-STK Schematics Figure 4-5. FPGA I/O AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 29 AT91CAP7A-STK Schematics Figure 4-6. LED’s/Push Buttons AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 30 AT91CAP7A-STK Schematics Figure 4-7. LCD Display AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 31 AT91CAP7A-STK Schematics Figure 4-8. USB/Serial/Data Flash AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 32 AT91CAP7A-STK Schematics Figure 4-9. Analog Sensors and Buffers 4-10 AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 33 AT91CAP7A-STK Schematics Figure 4-10. AT91CAP7 Power AT91CAP7A Starter Kit User Guide 4-11 8559A–CAP–09/08...
  • Page 34 AT91CAP7A-STK Schematics Figure 4-11. FPGA Power 4-12 AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 35 AT91CAP7A-STK Schematics Figure 4-12. FPGA Programming AT91CAP7A Starter Kit User Guide 4-13 8559A–CAP–09/08...
  • Page 36 AT91CAP7A-STK Schematics Figure 4-13. Power and Reset 4-14 AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...

  • Page 37: Revision History

    Section 5 Revision History Revision Hisory Change Request Document Comments 8559A First Issue AT91CAP7A Starter Kit User Guide 8559A–CAP–09/08...
  • Page 38 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...