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TMS320C6455
SPRS276M – MAY 2005 – REVISED MARCH 2012
Table 7-45. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
(see Figure 7-33 and Figure
NO.
1 t Output setup time, select signals valid to AAOE low
osu(SELV-AOEL)
2 t Output hold time, AAOE high to select signals invalid
oh(AOEH-SELIV)
10 t Delay time, AECLKOUT high to AAOE valid
d(EKOH-AOEV)
11 t Output setup time, select signals valid to AAWE low
osu(SELV-AWEL)
12 t Output hold time, AAWE high to select signals invalid
oh(AWEH-SELIV)
13 t Delay time, AECLKOUT high to AAWE valid
d(EKOH-AWEV)
(1) E = AECLKOUT period in ns for EMIFA
(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters
are programmed via the EMIFA CE Configuration registers (CEnCFG).
(3) Select signals for EMIFA include: ACEx, ABE[7:0], AEA[19:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[63:0].
AECLKOUT
ACEx
ABE[7:0]
AEA[19:0]/
ABA[1:0]
AED[63:0]
(A)
AAOE/ASOE
(A)
AAWE/ASWE
AR/W
(B)
AARDY
A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous
memory accesses.
B Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC).
Figure 7-33. Asynchronous Memory Read Timing for EMIFA
162 C64x+ Peripheral Information and Electrical Specifications
Memory Cycles for EMIFA Module
7-34)
PARAMETER
Setup = 1
1
1
1
10

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(1) (2) (3)
WS * E - 1.7
WH * E - 1.8
Strobe = 4
Byte Enables
Address
DEASSERTED
Copyright © 2005–2012, Texas Instruments Incorporated
TMS320C6455
www.ti.com
-720
-850
A-1000/-1000
UNIT
-1200
MIN MAX
RS * E - 1.5 ns
RS * E - 1.9 ns
1 7 ns
ns
ns
1.3 7.1 ns
Hold = 1
2
2
2
3
4
Read Data
10