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Table 7-70. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes)
BALL NUMBER
J2
H3
J1
J3
L1
L2
H2
M2
M1
L4
M4
K4
L3
L5
M3
N5
H4
H5
J5
J4
K3
K5
H1
N4
N3
M5
Using the RMII Mode of the EMAC
The Ethernet Media Access Controller (EMAC) contains logic that allows it to communicate using the
Reduced Media Independent Interface (RMII) protocol. This logic must be taken out of reset before being
used. To use the RMII mode of the EMAC follow these steps:
1. Enable the EMAC/MDIO through the Device State Control Registers.
– Unlock the PERCFG0 register by writing 0x0F0A 0B00 to the PERLOCK register.
– Set bit 4 in the PERCFG0 register within 16 SYSCLK3 clock cycles to enable the EMAC/MDIO.
– Poll the PERSTAT0 register to verify state change.
2. Initialize the EMAC/MDIO as needed.
3. Release the RMII logic from reset by clearing the RMII_RST bit of the EMAC Configuration Register
(see Section 3.4.5).
As described in the previous section, the RMII mode of the EMAC must be selected by setting
MACSEL[1:0] = 01b at device reset.
Copyright © 2005–2012, Texas Instruments Incorporated
DEVICE PIN NAME
URDATA0/MRXD0/RMRXD0
URDATA1/MRXD1/RMRXD1
URDATA2/MRXD2
URDATA3/MRXD3
URDATA4/MRXD4
URDATA5/MRXD5
URDATA6/MRXD6
URDATA7/MRXD7
UXDATA0/MTXD0/RMTXD0
UXDATA1/MTXD1/RMTXD1
UXDATA2/MTXD2
UXDATA3/MTXD3
UXDATA4/MTXD4
UXDATA5/MTXD5
UXDATA6/MTXD6
UXDATA7/MTXD7
URSOC/MRXER/RMRXER
URENB/MRXDV
UXENB/MTXEN/RMTXEN
URCLAV/MCRS/RMCRSDV
UXSOC/MCOL
UXCLAV/GMTCLK
URCLK/MRCLK
UXCLK/MTCLK/REFCLK
UXADDR3/GMDIO
UXADDR4/GMDCLK

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Product Folder Link(s):
SPRS276M – MAY 2005 – REVISED MARCH 2012
MII RMII
(MAC_SEL = (MAC_SEL =
00b) 01b)
MRXD0 RMRXD0
MRXD1 RMRXD1
MRXD2
MRXD3
MTXD0 RMTXD0
MTXD1 RMTXD1
MTXD2
MTXD3
MRXER RMRXER
MRXDV
MTXEN RMTXEN
MCRS RMCRSDV
MCOL
MRCLK
MTCLK RMREFCLK
MDIO MDIO
MDCLK MDCLK
C64x+ Peripheral Information and Electrical Specifications
TMS320C6455
TMS320C6455
GMII
(MAC_SEL =
10b)
MRXD0
MRXD1
MRXD2
MRXD3
MRXD4
MRXD5
MRXD6
MRXD7
MTXD0
MTXD1
MTXD2
MTXD3
MTXD4
MTXD5
MTXD6
MTXD7
MRXER
MRXDV
MTXEN
MCRS
MCOL
GMTCLK
MRCLK
MTCLK
MDIO
MDCLK
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