Motorola NXP SYMPHONY DSP56007 Technical Data Manual page 55

Freescale Semiconductor, Inc.
The Programmed Serial Clock Cycle, t
HDM0 and HRS bits of the HCKR (SHI Clock control Register).
The expression for t
where
• HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-by-
eight prescaler is operational. When HRS is set, the prescaler is bypassed.
• HDM5–HDM0 are the Divider Modulus Select bits.
• A divide ratio from 1 to 64 (HDM5–HDM0 = 0 to $3F) may be selected.
2
In I C mode, you may select a value for the Programmed Serial Clock Cycle from
6 ×
T
C
1024 ×
The DSP56007 provides an improved I
2
100 kHz I C bus protocol, the SHI in I
kHz. The actual maximum frequency is limited by the bus capacitances (C
up resistors (R
below)), and by the input filters.
Consideration for programming the SHI Clock Control Register (HCKR)—Clock
Divide Ratio: the master must generate a bus free time greater than T172 slave when
operating with a DSP56007 SHI I
The table below describes a few examples
Table 2-14 Considerations for Programming the SHI Clock control Register (HCKR)
Conditions to be Considered
Master
Oper-
Bus Load
ating
Freq.
C = 50 pF, 88 MHz 88 MHz
L
R = 2 kΩ
P
MOTOROLA
is:
2
I CCP
[ × × (
t = Tc 2 HDM[5:0]
2
I CCP
(HDM5–HDM0 = 2, HRS = 1)
(HDM5–HDM0 = $3F, HRS = 0).
T
C
), (which affect the rise and fall time of SDA and SCL, (see table
P
2
C slave.
Slave
Master Slave
Oper-
Filter Filter
ating
Mode Mode
Freq.
Bypassed Bypassed
Narrow Narrow
Wide Wide
DSP56007/D
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Serial Host Interface (SHI) I
, is specified by the value of the HDM5–
2
I CCP
) × ( × ( ) ) ]
+ 1 7 1 HRS – + 1
to
2
C bus protocol. In addition to supporting the
2
C mode supports data transfers at up to 1000
:
Resulting Limitations
Min.
T172 Perm-
Slave issible
t
2
I CCP
×
36 ns 56 T
C
×
60 ns 60 T
C
×
95 ns 66 T
C
Specifications
2
C Protocol Timing
),the pull-
L
Maximum
T172
2
I C Serial
Master
Frequency
41 ns 1010 kHz
66 ns 825 kHz
103 ns 634 kHz
2-31