Motorola NXP SYMPHONY DSP56007 Technical Data Manual page 3

Freescale Semiconductor, Inc.
FEATURES
Digital Signal Processing Core
• Efficient, object code compatible with the 24-bit DSP56000 core family engine
• Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at
88 MHz
• Highly parallel instruction set with unique DSP addressing modes
• Two 56-bit accumulators including extension byte
• Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
• Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles
• 56-bit addition/subtraction in 1 instruction cycle
• Fractional and integer arithmetic with support for multiprecision arithmetic
• Hardware support for block floating-point Fast Fourier Transforms (FFT)
• Hardware nested DO loops
• Zero-overhead fast interrupts (2 instruction cycles)
• Four 24-bit internal data buses and three 16-bit internal address buses for
simultaneous accesses to one program and two data memories
• Fabricated in high-density CMOS
Memory
• On-chip modified Harvard architecture, which permits simultaneous accesses
to program and two data memories
• Bootstrap loading from Serial Host Interface or External Memory Interface
Mode
PE
0
1
MOTOROLA
Table 1 Memory Configuration (Word width is 24 bits)
Program
ROM RAM ROM
6400 None 512
5120 1024 512
DSP56007/D
For More Information On This Product,
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X Data Y Data
RAM ROM
1024 512
1024 512
DSP56007
Features
Bootstrap
ROM
RAM
2176 52
1152 52
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