Motorola NXP SYMPHONY DSP56007 Technical Data Manual page 33

Freescale Semiconductor, Inc.
EXTERNAL MEMORY INTERFACE (EMI) DRAM TIMING
(C = 50 pF + 2 TTL Loads)
L
Table 2-8 External Memory Interface (EMI) DRAM Timing
No. Characteristics
41 Page Mode Cycle Time
42 RAS or RD Assertion to
Data Valid
43 CAS Assertion to Data
Valid
44 Column Address Valid
to Data Valid
45 CAS Assertion to Data
Active
46 RAS Assertion Pulse
1
Width
(Page Mode Access
Only)
47 RAS Assertion Pulse
Width
(Single Access Only)
48 RAS or CAS
Deassertation to RAS
Assertion
49 CAS Assertion Pulse
Width
50 Last CAS Assertion to
RAS Deassertation
(Page Mode Access
Only)
51 RAS or WR Assertion to
CAS Deassertation
52 RAS Assertion to CAS
Assertion
53 RAS Assertion to
Column Address Valid
MOTOROLA
Timing
Symbol Expression
Mode
t slow
PC
fast
t , slow 7
RAC
t fast 5
GA
T slow 3
CAC
fast 2
×
t slow 3
AA
×
fast 2
T
CLZ
t slow 3
RASP
+ n
fast 2
+ n
t slow 7
RAS
fast 5
t , slow 5
RP
T fast 3
CRP
T slow 3
CAS
fast 2
t slow 3
RSH
fast 2
T , slow 7
CSH
T fast 5
CWL
t slow 4
RCD
fast 3
×
t slow 3
RAD
×
fast 2
DSP56007/D
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External Memory Interface (EMI) DRAM Timing
50 MHz 66 MHz
Min Max Min Max Min Max
×
4 T 80 — 61
C
×
3 T 60 — 46
C
×
T – 16 — 124 —
C
×
T – 16 — 84 —
C
×
T – 10 — 50 —
C
×
T – 10 — 30 —
C
T + T – 7 — 63 —
C L
T + T – — 43 —
C L
7
0 0 — 0
×
T –11 209 — 156
C
× ×
4 T
C
×
T –11 149 — 110
C
× ×
3 T
C
×
T – 11 129 — 95
C
×
T – 11 89 — 65
C
×
T – 5 95 — 70
C
×
T – 5 55 — 40
C
×
T – 10 50 — 35
C
×
T – 10 30 — 20
C
×
T – 15 45 — 30
C
×
T – 15 25 — 15
C
×
T – 15 125 — 91
C
×
T – 15 85 — 61
C
×
T – 13 67 — 47
C
×
T – 13 47 — 32
C
T + T – 57 — 40
C H
13
T + T – 37 — 25
C H
13
Specifications
88 MHz
Unit
— 45.5 — ns
— 34.1 — ns
90 — 63.5 ns
60 — 40.8 ns
35 — 24.1 ns
20 — 12.7 ns
46 — 32.8 ns
30 — 21.4 ns
— 0 — ns
— 114 — ns
— 79.9 — ns
— 68.5 — ns
— 45.8 — ns
— 51.8 — ns
— 29.1 — ns
— 24.1 — ns
— 12.7 — ns
— 19.1 — ns
— 7.7 — ns
— 64.5 — ns
— 41.8 — ns
— 32.5 — ns
— 21.1 — ns
— 26.8 — ns
— 15.4 — ns
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