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Specifications
On-Chip Emulation (OnCE™) Timing
No.
248
DR Assertion Width
•
to recover from WAIT
•
to recover from WAIT and enter Debug
mode
249
DR Assertion to DSO (ACK) Valid (Enter Debug
mode) After Asynchronous Recovery from WAIT
State
250A
DR Assertion Width to Recover from STOP
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17 = 1
250B
DR Assertion Width to Recover from STOP and
enter Debug mode
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17 = 1
251
DR Assertion to DSO (ACK) Valid (Enter Debug
mode) After Recovery from STOP State
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17 = 1
T
Note:
1.
Maximum
L
2.
Periodically sampled, not 100% tested
DSCK
(input)
Figure 2-23 DSP56007 OnCE Serial Clock Timing
2-38
Freescale Semiconductor, Inc.
Table 2-17 OnCE Timing (Continued)
Characteristics
2
2
2
246
230
DSP56007/D
For More Information On This Product,
Go to: www.freescale.com
50/66/88 MHz
Min
15
12 T
13 T
+ 15
C
17 T
C
15
65548 T
15
20 T
15
13 T
65549 T
+ T
C
L
21 T
+ T
C
L
14 T
+ T
C
L
65553 T
+ T
C
L
25 T
+ T
C
L
18 T
+ T
C
L
231
232
Unit
Max
– 15
ns
C
—
ns
—
ns
+ T
ns
C
L
+ T
ns
C
L
+ T
ns
C
L
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
246
AA0277
MOTOROLA
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