Xilinx Zynq UltraScale+ User Manual page 9

X-Ref Target - Figure 1-2
VCU_APM_LIB
ALSA
MEDIA
ARM Cortex-A53-0
DisplayPort
TPG
SDI-Rx
Figure 1-2 shows the software state after the boot process has completed and the
individual applications have been started on the target processing units. The TRD does not
use virtualization and therefore does not run a hypervisor on the APU.
The APU application controls the following video data paths implemented in the PS and PL
(see Figure 1-3, page
• Capture pipeline capturing video frames into DDR memory from a high definition
media interface (HDMI source connected through the PL, an image sensor on an FMC
daughter card connected via MIPI CSI-2 RX Subsystem through the PL, serial digital
interface (SDI) source connected through the PL, and a Test Pattern Generator (TPG)
implemented inside the PL. Additionally, video can be sourced from a SATA drive, USB
3.0 device, or an SD card, which is also used as a boot device.
• Processing (memory-to-memory) pipeline includes VCU encode/decode. Video frames
are read from DDR memory, processed by the VCU, and written back to memory.
• Display pipeline reading video frames from memory and sending them to a monitor via
the DisplayPort TX Controller inside the PS, SDI Transmitter Subsystem through the PL
or the HDMI Transmitter Subsystem through the PL. The DisplayPort TX Controller
supports two layers—one for video, the other for graphics and the SDI Transmitter
Subsystem with mixer IP support up to four layers and HDMI Transmitter Subsystem
with mixer IP supports up to eight such layers. The graphics layer is rendered by the GPU.
• Audio Capture pipeline to capture audio frames from HDMI-RX, SDI-RX and I2S-RX
interfaces.
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
VCU_GST_APP VCU_QT
VCU_GST_LIB
V4L2
DMABUF
ARM Cortex-A53-1
GPU
HDMI-Tx HDMI-Rx
SDI-Tx PCIe
Figure 1-2: Key Reference Design Components
11):
www.xilinx.com
PCIe_TRANSCODE
VCU_VIDEO_LIB
DRM
U10
ARM Cortex-A53-2
USB
SATA
VCU
CSI-Rx
XDMA I2S-Rx
SCD
Chapter 1: Introduction
PCIe_LIB
pcie_ep_client
ARM Cortex-A53-3
SD
PL DDR
I2S-Tx
X22060-041719
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