Xilinx Zynq UltraScale+ User Manual page 69

HDMI Audio RX Pipeline
The HDMI audio RX pipeline is shown in
X-Ref Target - Figure 5-12
Video
PHY
MIPI to
RX SS
Rx Data
This pipeline consists of two components, each of them controlled by the APU through an
AXI4-Lite base register interface:
• The Video PHY Controller is shared with the HDMI RX and HDMI TX pipelines. Refer to
HDMI RX Capture Pipeline
• The HDMI RX Subsystem is shared with the HDMI RX pipeline. Refer to
Capture Pipeline
• The Audio Formatter provides high-bandwidth direct memory access between memory
and AXI4-Stream target peripherals. Initialization, status, and management registers are
accessed through an AXI4-Lite slave interface. It is configured with both read and write
interface enabled for a maximum of two audio channels and interleaved memory
packing mode with memory data format configured as AES to PCM.
The Audio Engineering Society (AES) standard was developed for the exchange of digital
Note:
audio signals between professional audio devices.
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
HDMI Audio RX Pipeline
32
40
HDMI RX Audio
40
32
SS Formatter 1
40
I2S RX Audio
32
SS Formatter 2
AXI-Lite AXI-Stream
Figure 5-12: HDMI Audio RX Pipeline
for more information on the VPHY and its configuration.
for more information on the VPHY and its configuration.
www.xilinx.com
Chapter 5: Hardware Platform
Figure 5-12.
32
AXI-MM
PL PS
HPM0/1
128
HP
128
X21948-042619 X21948-112718
HDMI RX
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