Address Map - Xilinx Zynq UltraScale+ User Manual

I2S Audio Pipeline
The I2S Transmitter and Receiver cores are soft Xilinx IP cores, which make easy to
implement inter-IC-sound (I2S) interfaces used to connect audio devices for transmitting
and receiving PCM audio. The I2S Transmitter and I2S Receiver cores provide an easy way to
interface the I2S based audio DAC/ADC. These IPs require minimal register programming
and support any audio sampling rates. For more information refer to the I2S Transmitter and
I2S Receiver LogiCORE IP Product Guide (PG308)
PL_DDR
The Zynq UltraScale+ MPSoC VCU DDR4 Controller is an application-specific DDR
controller that is only supported for use with the Zynq UltraScale+ MPSoC VCU
(H.264/H.265 Video Codec unit).

Address Map

Table 5-1 shows the address map for various IP blocks used in PL for the VCU TRD
full-fledged design.
Table 5-1: Address Map for IP Blocks of the VCU TRD Full-fledged Design
AXI Interrupt Controller
HDMI I2C Controller
MIPI CSI-2 Receiver Subsystem
Sensor I2C Controller
Sensor Demosaic
HDMI Frame Buffer Read
HDMI Frame Buffer Write 0
TPG Frame Buffer Write
CSI Frame Buffer Write
HDMI Frame Buffer Write 1
HDMI Frame Buffer Write 2
HDMI Frame Buffer Write 3
HDMI Frame Buffer Write 4
HDMI Frame Buffer Write 5
HDMI Frame Buffer Write 6
Gamma LUT
HDMI 1.4/2.0 Receiver Subsystem v2.0
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
IP Core
www.xilinx.com
Chapter 5: Hardware Platform
[Ref 24].
Base Address
0x00A0052000
0x00A0050000
0x00A00F0000
0x00A0051000
0x00A0250000
0x00A0040000
0x00A0010000
0x00A00C0000
0x00A0260000
0x00A02B0000
0x00A02C0000
0x00A0280000
0x00A0290000
0x00A02A0000
0x00A02D0000
0x00A0270000
0x00A0000000
Send Feedback
Offset
4K
4K
64K
4K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
72