Video Pipelines - Xilinx Zynq UltraScale+ User Manual

Video Pipelines

A live-capture/file-src element receives frames from an external source or produces video
frames internally. The captured video frames are written into memory.
A processing element reads video frames from memory, does certain processing, and then
writes the processed frames back into memory.
A display element reads video frames from memory and sends the frames to a sink. In cases
where sink is displayed, this pipeline is also referred to as display pipeline.
TPG Capture Pipeline
The TPG capture pipeline is shown in
X-Ref Target - Figure 5-3
VTC
Video Timing
This pipeline consists of three main components, each of them controlled by the APU via an
AXI4-Lite based register interface:
• The Video Timing Controller (VTC) generates video timing signals including horizontal
and vertical sync and blanking signals. The timing signals are converted to AXI4-Stream
using the video-to-AXI4-Stream bridge with the data bus tied off. The video timing over
AXI4-Stream bus is connected to the input interface of the TPG, thus making the TPG
behave like a timing-accurate video source with a set frame rate as opposed to using
the free-running mode.
• The Video Test Pattern Generator (TPG) can be configured to generate various test
patterns including color bars, zone plates, moving ramps, moving boxes and more. The
color space format is configurable and set to YUV 4:2:0 in this design. For more
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
Figure
TPG Capture Pipeline
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AXIS
AXI-S AXI-MM
Figure 5-3: TPG Video Capture Pipeline
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