Clocking - Xilinx Zynq UltraScale+ User Manual

• The DP TX display pipeline (in PS) consists of the PS DisplayPort controller. DisplayPort
direct memory access (DPDMA) fetches both graphics and the video layer from
memory. The DisplayPort controller processes data and sends it out to external display
devices using the DisplayPort Standard.
• The SDI TX display pipeline (in PL) is controlled by the Video Mixer, which fetches the
video layer from memory and sends to the SDI TX Subsystem. The SDI TX Subsystem
processes data and sends it out to an external display device.
• The USB universal video class (UVC) capture pipeline (in PS) consists of the USB
Controller, and takes recorded video files and writes the data into DDR memory.
• The Ethernet 10G output pipeline (in PL) consists of AXI DMA IP that reads data from
memory followed by the 10G/25G Ethernet Subsystem IP that transmits data to
Ethernet.
• The audio output pipeline (in PL) consists of Audio Formatter IP that reads audio data
from memory and sends it out to the HDMI TX Subsystem IP, which sends it to the
output device.
• The design uses the PCIe® Endpoint block with high-performance XDMA for data
transfers between the host system memory and the Endpoint. In the card-to-host
direction, the XDMA block moves data from the Endpoint PS DDR to the host memory
through PCIe.
The block diagram highlights these two partitions of the design:
• The hardware Base Platform, which consists of all the capture and display pipelines and
VCU processing pipelines. (This part of the design is fixed with respect to the SDx™
tool.)
• The hardware accelerator and corresponding data motion network. (This part of the
design is generated by the SDx tool and is automatically added into the PL design.)

Clocking

This section describes the clocking mechanism used in the TRD. The primary clock is
sourced from si570_user sources that provide a 300 MHz reference clock to the PL. A
mixed-mode clock manager (MMCM) block in PL uses the si570 clock as a primary input
clock and generates the reference clock for the VCU PLL, AXI4-Lite clock, and video pixel
clock. The VCU PLL generates the core clock and MCU clock based on the input reference.
PL_CLK0 from the processing system is also used as the AXI4-Lite clock for some
peripherals.
The USER_MGT_SI570_CLOCK is used as source for the DRU_CLK/SDI GT reference clock.
Figure 5-2 shows the clocking mechanism used for the TRD. The 125 MHz mig clock is used
as PL DDR ref clock. The VCU_DDR4 soft IP generates the 250 MHz user_clk required for
processing the data.
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
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