Xilinx Zynq UltraScale+ User Manual page 8

DisplayPort controller interface up to 4K (3840 x 2160) 30 FPS
°
• High-speed peripherals
PCIe root complex and Endpoint (Gen1 or Gen2 x1, x2, and x4 lanes)
°
USB 3.0/2.0 with host, device and on-the-go (OTG) modes
°
SATA 3.1 host
°
• Low-speed peripherals
Gigabit Ethernet, controller area network (CAN), universal asynchronous
°
receiver-transmitter (UART), Serial Peripheral Interface (SPI), Quad SPI, NAND flash
memory, Secure Digital embedded Multimedia Card (SD/eMMC), inter IC (I2C), and
general purpose I/O (GPIO)
• Platform management unit (PMU)
• Configuration security unit (CSU)
• 6-port DDR controller with error correction code (ECC), supporting x32 and x64
DDR4/3/3L and LPDDR4/3
Reference Design Overview
The MPSoC has a heterogeneous processor architecture. The TRD makes use of multiple
processing units available inside the PS using this software configuration:
The APU consists of quad Arm Cortex-A53 cores configured to run in SMP Linux mode. The
main task of the application is to configure and control the video pipelines using a Qt v5.9.4
based graphical user application. See
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
Figure 1-2.
www.xilinx.com
Chapter 1: Introduction
8
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