Key Features - Xilinx Zynq UltraScale+ User Manual

The remaining blocks are common to all designs. See
Details for more details.
The reference design targets the ZCU106 evaluation board. The board has an onboard
HDMI transmitter and receiver connector, SDI transmitter and receiver connector, and a
DisplayPort connector interface. The evaluation board provides the HDMI reference clock,
data recovery unit (DRU) clock, and the reference clock for the design. The PS_REF_CLK is
sourced from another dedicated clock generator present on the evaluation board.
Figure 1-4 shows the block diagram of the TRD along with the board components.
X-Ref Target - Figure 1-4
Live video source
(HDMI/TPG/SDI/MIPI)
Live audio source
(HDMI/SDI/I2S)
File/streaming source
Figure 1-4: High-Level Block Diagram of ZCU106 Device Architecture

Key Features

Target platforms and extensions:
• ZCU106 evaluation board (see ZCU106 Evaluation Board User Guide (UG1244))
• Optional: Leopard Imaging LI-IMX274MIPI-FMC image sensor daughter card
• SDI Receiver - Blackmagic Design Teranex Mini HDMI to 12G converter
• SDI Transmitter - Blackmagic Design Teranex Mini 12G to HDMI converter
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
PS DDR Memory
Capture
Processing
Pipeline
Pipeline
(Audio/Video
PS CLK
(Si5341) SFP_SI5328_out
33.33 MHz
www.xilinx.com
Chapter 1: Introduction
Chapter 2, Targeted Reference Design
PL DDR Memory
(HDMI/SDI/DP)
Render
Pipeline
(Audio/Video
(HDMI/SDI/DP/I2S
Si5328
156.25 MHz
Send Feedback
Video Sink
Audio Sink
X19301-041719
[Ref 2]
[Ref 3]
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