Reset - Xilinx Zynq UltraScale+ User Manual

The audio design uses pl_clk1 as the Video Pixel clock (instead of MMCM output) for both TX
Note:
and RX pipelines. The Ethernet 10G design uses the SPF_SI5328_OUT clock from the board as the
DRU clock, because USER_MGT_SI570_CLOCK is used by the Ethernet Subsystem as the GT reference
clock.
X-Ref Target - Figure 5-2
MIG Clock
VCU DDR4
Controller
DRU/SDI GT reference clock
Ethernet GT reference clock
Si570_user
MMCM
Processing
System

Reset

A synchronous reset mechanism is used in the TRD. PL_RESET0 is used as a master reset
signal. Interconnect and peripheral reset signals are generated using proc_sys_rst IP in the
PL. The VCU Reset in PCIe design is gated with the link_up signal of the PCIe Endpoint block.
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
User Clk
Video Pixel Clock
MIPI dphy Clock
VCU Reference Clock
pl_clk1
Audio Clock
pl_clk0
Figure 5-2: Clocking Mechanism for the TRD
www.xilinx.com
Input/Capture
I2S Rx
HDMI Rx
SDI Rx
MIPI Rx
TPG
Audio
Formatter Rx
Ethernet Rx
Chapter 5: Hardware Platform
Output/Display
HDMI Tx
SDI Tx
Audio
Formatter Tx
Ethernet Tx
I2S Tx
Processing
VCU
Hardware
Accelerator
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