Xilinx Zynq UltraScale+ User Manual page 68

Ethernet 10G Output Pipeline
The Ethernet 10G output pipeline is shown in
X-Ref Target - Figure 5-11
Ethernet 10G Output/Capture Pipeline
Ethernet 10G/25G
Subsystem
AXI-Lite
This pipeline consists of two main components—the 10G/25G high speed Ethernet
Subsystem and AXI DMA, each shared with the Ethernet 10G input/capture pipeline. Refer
to Ethernet 10G Input/Capture Pipeline
each component.
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
32
AXI
64 64
DMA
AXI-Stream
Figure 5-11: Ethernet 10G Output Pipeline
for more information and for the configuration of
www.xilinx.com
Chapter 5: Hardware Platform
Figure 5-11.
128
128
AXI-MM
PL
PS
HPM0/1
HP0
X21947-042419 X21947-120318
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