Interrupt Map - Xilinx Zynq UltraScale+ User Manual

Interrupt Map

Table 5-6 shows interrupt ID mapping for the VCU TRD full-fledged design.
Table 5-6: Interrupt ID Map for Full-fledged Design
HDMI CTL IIC
HDMI Frame Buffer Read
HDMI Frame Buffer Write_0
HDMI Frame Buffer Write_1
HDMI Frame Buffer Write_2
HDMI RX
HDMI TX
Interrupt Controller
MIPI Frame Buffer Write
MIPI RX SS
Sensor IIC
TPG Frame Buffer Write
VCU
Video mixer
Video Physical controller
HDMI CTL IIC
AXI Interrupt Controller used to accommodate all the interrupts as total number of PL-PS
Note:
interrupts exceeds 16 in the design.
Table 5-7 shows interrupt ID mapping for VCU audio design.
Table 5-7: Interrupt ID Map for VCU Audio Design
HDMI I2C Controller
HDMI 1.4/2.0 Transmitter Subsystem v2.0
Video Mixer
HDMI Frame Buffer Read
HDMI Frame Buffer Write
HDMI 1.4/2.0 Receiver Subsystem v2.0
Audio Formatter MM2S 1
Audio Formatter S2MM 1
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
IP Core
IP Core
www.xilinx.com
Chapter 5: Hardware Platform
Interrupt ID
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Interrupt ID
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93
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89
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105
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