Chapter 4: System Considerations; Boot Process - Xilinx Zynq UltraScale+ User Manual

System Considerations
This chapter describes the boot process and address mapping.

Boot Process

The reference design uses a non-secure boot flow and SD boot mode. The sequence
diagram in Figure 4-1
components are loaded and executed.
X-Ref Target - Figure 4-1
Release
PMU
CSU
Load PMU
CSU
FW
APU
PL
Time
The platform management unit (PMU) is responsible for handling primary pre-boot tasks
and is the first unit to wake up after power-on reset (POR). After the initial boot process, the
PMU continues to run and is responsible for handling various clocks and resets of the
system as well as system power management. In the pre-configuration stage, the PMU
executes the PMU ROM and releases the reset of the configuration security unit (CSU). It
then enters the PMU server mode where it monitors power.
The CSU handles the configuration stages and executes the boot ROM as soon as it comes
out of reset. The boot ROM determines the boot mode by reading the boot mode register,
it initializes the on-chip memory (OCM), and reads the boot header. The CSU loads the PMU
firmware into the PMU RAM and signals to the PMU to execute the firmware, which
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
shows the exact steps and order in which the individual boot
Load FSBL
FSBL ATF
Figure 4-1: Boot Flow Sequence
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Power Management
Tamper Monitoring
U-boot Linux Kernel Rootfs
PL Bitstream
Chapter 4
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