Xilinx Zynq UltraScale+ User Manual page 59

information, see the Video Test Pattern Generator LogiCORE IP Product Guide (PG103)
[Ref 9].
• The Video Frame Buffer Write IP provides high-bandwidth direct memory access
between memory and AXI4-Stream video type target peripherals, which support the
AXI4-Stream Video protocol. In this pipeline, the IP takes AXI4-Stream input data from
the TPG and converts it to memory-mapped AXI4 format. The output is connected to
the HP1 high performance PS/PL interface via an AXI interconnect. For each video
frame transfer, an interrupt is generated. A GPIO is used to reset the core between
resolution changes. For more information refer to the Video Frame Buffer Read and
Video Frame Buffer Write LogiCORE IP Product Guide (PG278)
HDMI RX Capture Pipeline
The HDMI receiver capture pipeline is shown in
X-Ref Target - Figure 5-4
40
Video
40
PHY
40
Rx Data
This pipeline consists of four main components, each of them controlled by the APU via an
AXI4-Lite base register interface:
• The Video PHY Controller (VPHY) enables plug-and-play connectivity with Video
Transmit or Receive Subsystems. The interface between the media access control (MAC)
and physical (PHY) layers are standardized to enable ease of use in accessing shared
gigabit-transceiver (GT) resources. The data recovery unit (DRU) is used to support
lower line rates for the HDMI protocol. An AXI4-Lite register interface is provided to
enable dynamic accesses of transceiver controls/status. For more information refer to
the Video PHY Controller LogiCORE IP Product Guide (PG230)
• The HDMI Receiver Subsystem (HDMI RX) interfaces with PHY layers and provides
HDMI decoding functionality. The subsystem is a hierarchical IP that bundles a
collection of HDMI RX-related IP subcores and outputs them as a single IP. The
subsystem receives the captured TMDS data from the video PHY layer. It then extracts
the video stream from the HDMI stream and in this design converts it to an
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
HDMI Rx Capture Pipeline
32
HDMI Rx VPSS
48
SS Scaler
AXI-S AXI-MM
Figure 5-4: HDMI Video Capture Pipeline
www.xilinx.com
Chapter 5: Hardware Platform
Figure 5-4.
Frmbuf
48 32
Write
AXI-Lite
[Ref 10].
PL PS
HPM0/1
32
128 HP1 HP1
X20149-042519
[Ref 11].
Send Feedback
59