Xilinx Zynq UltraScale+ User Manual page 70

HDMI Audio TX Pipeline
This pipeline consists of three main components—Video PHY Controller, HDMI RX
Subsystem, and Audio Formatter, each shared with the audio input/capture pipeline. Refer
to the following sections for more information and for the configuration of each
component:
• Video PHY Controller (see
• HDMI RX Subsystem (see
• Audio Formatter (see
HDMI RX Subsystem IP is available from Xilinx. HDMI 1.4/2.0 Receiver Subsystem v3.1 is the
Note:
current version as of this printing.
Accelerator Processing Pipeline
The accelerator processing pipeline is shown in
dummy SDx accelerator is entirely generated by the SDSoC™ tool based on the C code
description. The accelerator function (which is simply copying the input data) is translated
to RTL using the Vivado® tool HLS compiler. The data motion network to transfer video
buffers to and from memory is inferred automatically by SDSoC tool compiler.
X-Ref Target - Figure 5-13
Accelerator
Control
The HLS generated accelerator is controlled by an accelerator adaptor that drives all inputs
and captures all outputs. The accelerator adapter has memory-mapped AXI interfaces to
transfer data to and from the HP port and the accelerator. Both HP ports used by the VCU
encoder and decoder are multiplexed with the accelerator adapter. For AXI4-Lite control
interfaces, a HPM port is used.
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
HDMI RX Capture
HDMI RX Capture
HDMI Audio RX
SDx
(HLS)
Accelerator
Adapter
AXI-Lite
Figure 5-13: Accelerator Processing Pipeline
www.xilinx.com
Chapter 5: Hardware Platform
Pipeline)
Pipeline)
Pipeline)
Figure 5-13. The processing pipeline with a
FIFO AXI-MM
PL PS
HPM0/1
128
HP2/3
128
X21950-051719
Send Feedback
70