Xilinx Zynq UltraScale+ User Manual page 77

Table 5-7: Interrupt ID Map for VCU Audio Design (Cont'd)
Audio Formatter MM2S 2
Audio Formatter S2MM 2
I2S transmitter
I2S receiver
Interrupt Controller
Table 5-8 shows interrupt ID mapping for an Ethernet 10G design.
Table 5-8: Interrupt ID Map for Ethernet 10G Design
HDMI I2C Controller
HDMI 1.4/2.0 Transmitter Subsystem v2.0
Video Mixer
HDMI Frame Buffer Read
HDMI Frame Buffer Write 0
HDMI 1.4/2.0 Receiver Subsystem v2.0
Video PHY Controller
VCU
DMA S2MM
DMA MM2S
HDMI Frame Buffer Write 1
HDMI Frame Buffer Write 2
Table 5-9 shows interrupt ID mapping for an SDI design.
Table 5-9: Interrupt ID Map for SDI Design
Audio Formatter mm2s
Audio Formatter s2mm
Frame Buffer Read
Frame Buffer Read
Frame Buffer Write
Frame Buffer Write
SDI Audio Extract
SDI RX
SDI TX
Zynq UltraScale+ VCU TRD User Guide
UG1250 (v2019.1) May 29, 2019
IP Core
IP Core
IP Core
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Chapter 5: Hardware Platform
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