Clock Architecture - Symmetricom XLi User Manual

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Clock Architecture

The following figures provide a simplified view of the XLi's clock architecture.
Aux Ref Aux Ref - 1/5/10 MHz
1 PPS A
1 PPS B
Code Input
Figure 1: Functional Timing Block Diagram
XLi Time & Frequency System
XLi-man, Issue 8, 6/17/2008, Rev. H
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1 PPS Timing Select
Time and Clock
Recovery
Code Input
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16.384 MHz Osc. PLL
Phase Measurement
Clock DPLL
DAC Select
DAC
10 MHz Osc.
200 MHz PLL
Phase Compare
Clock Machine
Code Generation
Rate Generation
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2
1
5
1 PPS Output
Code Output
Rate Output
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3