Overview Of Embedded Software Design Guidelines For Soc Fpga Design - Intel Cyclone V Design Manuallines

1. Overview of the Design Guidelines for Cyclone
AN-796 | 2018.06.18
1.4. Overview of Embedded Software Design Guidelines for SoC
FPGA Design
Table 4. Embedded Software: Design Guidelines Overview
Stages of the Embedded Software
Design Flow
Operating System (OS) considerations
Boot Loader considerations
Boot and Configuration Design
Considerations
HPS ECC Considerations
HPS SDRAM Considerations
®
V SoC FPGAs and Arria
Guidelines
OS considerations to meet your
application needs, including real time,
software reuse, support and ease of
use considerations
Boot loader considerations to meet
your application needs. including GPL
requirements, and features.
Boot source, boot clock, boot fuses,
configuration flows
ECC for external SDRAM interface, L2
cache data memory, flash memory
Using Preloader to debug HPS SDRAM,
Accessing the HPS SDRAM
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
®
V SoC FPGAs
Links
Selecting an Operating System for Your
Application on page 52
Choosing Boot Loader Software
page 58
Boot and Configuration Design
Considerations on page 28
HPS ECC Design Considerations
page 61
HPS SDRAM Considerations
63
on
on
on page
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