Intel Cyclone V Design Manuallines page 41

4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
required by the HPS EMAC. An FPGA PLL can be used to provide the 2.5 MHz and 25
MHz
TX_CLK
glitch-free.
Note: Refer to the
this implementation.
4.5.1.2.3. Adapting to RMII
It is possible to adapt the MII HPS EMAC PHY signals to an RMII PHY interface at the
FPGA I/O pins using logic in the FPGA.
GUIDELINE: Provide a 50MHz
An RMII PHY uses a single 50 MHz reference clock (
receive data and control. Provide the 50 MHz
source, a generated clock from the FPGA fabric, or from a PHY capable of generating
the
REF_CLK
GUIDELINE: Adapt the transmit and receive data and control paths.
The HPS EMAC PHY interface exposed in the FPGA fabric is MII, which requires
separate transmit and receive clock inputs of 2.5 MHz and 25 MHz for 10 Mbps and
100 Mbps modes of operation, respectively. Both transmit and receive datapaths are
4-bits wide. The RMII PHY uses the 50 MHz
datapaths and at both 10 Mbps and 100 Mbps modes of operation. The RMII transmit
and receive datapaths are 2-bits wide. At 10 Mbps, transmit and receive data and
control are held stable for 10 clock cycles of the 50 MHz
adaptation logic in the FPGA fabric to adapt between the HPS EMAC MII and external
RMII PHY interfaces: 4-bits @ 25 MHz/2.5 MHz to/from 2-bits@ 50 MHz, 10x
oversampled in 10 Mbps mode.
GUIDELINE: Provide a glitch-free clock source on the HPS EMAC MII
tx_clk_in
The HPS component's MII interface requires a 2.5/25 MHz transmit clock on its
emac[0,1,2]_tx_clk_in
must be done glitch free as required by the HPS EMAC. An FPGA PLL can be used to
provide the 2.5 MHz and 25 MHz transmit clock along with an
select between counter outputs glitch-free.
Related Information
Embedded Peripherals IP User Guide
4.5.1.2.4. Adapting to SGMII
It is possible to adapt the GMII HPS EMAC PHY signals to an SGMII PHY interface at
the FPGA transceiver I/O pins using logic in the FPGA and the multi-gigabit transceiver
I/O. While it is possible to design custom logic for this adaptation, this section
describes using Platform Designer (Standard) adapter IP.
along with an
ALTCLKCTRL
Cyclone V RGMII Example Design
REF_CLK
.
clock input.
input port, and the switch between 2.5 MHz and 25 MHz
block to select between counter outputs
for hardware and software example of
source.
) for both transmit and
REF_CLK
either with a board-level clock
REF_CLK
for both its transmit and receive
REF_CLK
REF_CLK
ALTCLKCTRL
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
. You must provide
block to
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