Intel Cyclone V Design Manuallines page 11

2. Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS Subsystems
AN-796 | 2018.06.18
Figure 1. HPS-FPGA Bridges
Key:
H2F: HPS-to-FPGA
LWH2F: Lightweight HPS-to-FPGA
F2H: FPGA-to-HPS
F2S: FPGA-to-SDRAM
2.1.1.1. Lightweight HPS-to-FPGA Bridge
GUIDELINE: Use the lightweight HPS-to-FPGA bridge to connect IP that
needs to be controlled by the HPS.
The lightweight HPS-to-FPGA bridge allows masters in the HPS to access memory-
mapped control slave ports in the FPGA portion of the SoC device. Typically, only the
MPU inside the HPS accesses this bridge to perform control and status register
accesses to peripherals in the FPGA.
GUIDELINE: Do not use the lightweight HPS-to-FPGA bridge for FPGA
memory. Instead use the HPS-to-FPGA bridge for memory.
When the MPU accesses control and status registers within peripherals, these
transactions are typically strongly ordered (non-posted). By dedicating the lightweight
HPS-to-FPGA bridge to register accesses, the access time is minimized because
bursting traffic is routed to the HPS-to-FPGA bridge instead.
The lightweight HPS-to-FPGA bridge has a fixed 32-bit width connection to the FPGA
fabric, because most IP cores implement 32-bit control and status registers. However,
Platform Designer (Standard) can adapt the transactions to widths other than 32 bits
within the FPGA-generated network interconnect.
LWH2F Bridge
FPGA Fabric
32 bit
H2F Bridge
32/64/128 bit
F2H Bridge
32/64/128 bit
DMA
F2S Interface
All Other All Other
L3 Slaves L3 Masters
L3 Slave L3 Master
Peripheral Switch Peripheral Switch
L3 Interconnect
Main Switch
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
MPU
ACP
SRAM
Controller
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