Intel Cyclone V Design Manuallines page 72

Document Version
2017.02.20
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
72
• "Board Design Guidelines for SoC FPGAs" chapter:
— RGMII supported by HPS dedicated I/O
— Guidelines added:
• If your design uses QSPI flash with 4-byte addressing, design the
board to ensure that the QSPI flash is reset or power-cycled whenever
the HPS is reset.
• If your SPI peripheral requires the SPI master slave select to stay low
during the entire transaction period, consider using GPIO as slave
select, or configure the SPI master to assert slave select during the
transaction.
• Ensure that the SD/MMC card is reset whenever the HPS is reset.
• For bare-metal applications, avoid using a QSPI flash device larger
than 16 MB
• With a QSPI device larger than 16 MB, use QSPI extended 4-byte
addressing commands if supported by the device
• "Embedded Software Design Guidelines for SoC FPGAs" chapter:
— Reference DTB for NAND-based boot no longer supplied
— Clarify NAND flash interface type required for booting support
Initial Release
B. Additional Information
AN-796 | 2018.06.18
Description