Intel Cyclone V Design Manuallines page 37

4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
GUIDELINE: When selecting a PHY device, consider the desired Ethernet rate,
available I/O and available transceivers; PHY devices that offer the skew
control feature; and device driver availability.
Note: Refer to the device drivers available for your OS of choice or the Linux device driver
provided with the Cyclone V/ Arria V SoC development kit (Golden System Reference
Design)
The Cyclone V/Arria V SoC Hard Processor System (HPS) can connect its embedded
Ethernet MAC (EMAC) PHY interfaces directly to industry standard Gigabit Ethernet
PHYs using the RGMII interface at any supported I/O voltage using the HPS Dedicated
I/O pins. These voltages typically include 1.8V, 2.5V and 3.0V. If the HPS Dedicated
I/O pins are used for the PHY interface, then no FPGA routing resources are used and
timing is fixed, simplifying timing on the interface. This document describes the design
guidelines for RGMII, the most typical interfaces.
You can also connect PHYs to the HPS EMACs through the FPGA fabric using the GMII
and MII bus interfaces for Gigabit and 10/100 Mbps access respectively. A GMII-to-
SGMII adapter is also available to automatically adapt to transceiver-based SGMII
optical modules.
Note: Due to an erratum in the Cyclone V/Arria V SoC device, the RMII PHY interface is not
supported when routing through the HPS Dedicated I/O. RMII interface however is
supported when routing through the FPGA fabric.
Related Information
• "Introduction to the HPS Component" chapter of the Cyclone V Hard Processor
System Technical Reference Manual
• "Introduction to the HPS Component" chapter of the Arria V Hard Processor
System Technical Reference Manual
• Golden System Reference Design (GSRD) User Manuals
4.5.1.1. PHY Interfaces Connected Through HPS Dedicated I/O
This section discusses design considerations for RGMII PHY interface through the HPS
Dedicated I/O.
4.5.1.1.1. RGMII
Reduced Gigabit Media Independent Interface (RGMII) (Reduced GMII) is the most
common interface as it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection
speeds at the PHY layer. RGMII uses four-bit wide transmit and receive datapaths,
each with its own source synchronous clock. All transmit data and control signals are
source synchronous to
synchronous to
For all speed modes,
sourced by the PHY. In 1000 Mbps mode,
Data Rate (DDR) signaling is used. In
10 Mbps and 100 Mbps modes,
respectively, and rising edge Single Data Rate (SDR) signaling is used.
, and all receive data and control signals are source
TX_CLK
.
RX_CLK
is always sourced by the MAC, and
TX_CLK
TX_CLK
and
TX_CLK RX_CLK
and are 2.5 MHz and 25 MHz,
RX_CLK
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
is always
RX_CLK
are 125 MHz, and Dual
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