I 2 C Interface Design Guidelines; Spi Interface Design Guidelines - Intel Cyclone V Design Manuallines

4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
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4.5.7. I C Interface Design Guidelines
GUIDELINE: Instantiate the open-drain buffer when routing I
through the FPGA fabric.
When routing I
FPGA fabric (
inverted. Thus, when you want to drive a logic level zero onto the I
are high. This implementation is useful as they can be used to tie to an output enable
of a tri-state buffer directly. You must use the
buffer.
GUIDELINE: Ensure that the pull-ups are added to the external
signals in the board design.
Because the I
bus is pulled high when no device on the bus is pulling it low.
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Figure 5. I C Wiring to FPGA pins

4.5.8. SPI Interface Design Guidelines

GUIDELINE: Consider routing SPI slave signals to FPGA fabric
Due to an erratum in the Cyclone V/Arria V SoC device, the SPI output enable is not
connected to the SPI HPS pins. As a result, the HPS
stated by setting the
Routing the SPI Slave signals to FPGA exposes the output enable signal and allows you
to connect it to an FPGA tri-state pin.
GUIDELINE: If your SPI peripheral requires the SPI master slave select to
stay low during the entire transaction period, consider using GPIO as slave
select, or configure the SPI master to assert slave select during the
transaction.
By default, the SPI master is configured with
= 0, which makes the Cyclone V or Arria V HPS SPI master deassert the slave select
signal between each data word. Set
make the SPI master assert slave select for the entire duration of the transfer.
2
C signals through the FPGA, note that the I
,
i2c*_out_data i2c*_out_clk
2
C signals are open drain, pull-ups are required to make sure that the
HPS FPGA Fabric
i2c*_out_data
i2c*_in_data
i2c*_out_clk
i2c*_in_clk
bit (bit
slv_oe
2
) are not open-drain and are logic level
to implement the open-drain
altiobuf
FPGA I/O
SPIS_TXD
) in the register to
10 ctrlr0
ctrlr0.scph
to 1 and
ctrlr0.scph
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
2
C signals
C pins from the HPS to the
2
C bus, these pins
and
SDA SCL
pin cannot be tri-
.
1
= 0 and
ctrlr0.scpol
to 1, to
ctrlr0.scpol
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